Appendix E
In this chapter · 7 sections
Glossary, Phase-Gate Timeline & Learning/Community Map
Three reference layers for the bench — the terms of art, an applied dependency-schedule exercise, and the primary sources and communities that keep a project team’s decisions current.
What you'll decide here
- Use the thematic glossary as a decoder ring, with the full A–Z index at /glossary. The third column names the canonical chapter; jump there when the one-line definition does not close the decision.
- Read phase gates against Chapter 2.1’s dependency network: calculate float to the same first-productive-run milestone. In the applied exercise, test whether delaying building readiness or accelerating transformer delivery changes that date.
- Treat the month ranges as illustrative package allowances, not commitments. Replace them with the serving utility’s milestones and equipment quotes; retain land, permits and construction wherever a retrofit or colocation contract still requires them.
- Work the learning/community map as a maintenance plan: pick one certification track per discipline on your team, put the two or three anchor conferences on the calendar, and subscribe to the feeds so the figures in this guide are corrected by primary sources, not by a competitor's outage.
This appendix is the reference layer the rest of the guide leans on, and it does three jobs. First, the glossary — four thematic tables resolving the terms of art the body chapters lean on hardest, with the site's full A–Z decoder at the glossary, from efficiency ratios (PUE, WUE, ERF) through utilization metrics (MFU, MBU, goodput) to fabric and packaging vocabulary (NVLink domain, CoWoS, HBM, RoCE) and the program-management primitives (SU, ETTR, phase gate). Each entry names the chapter that owns the full treatment, so the glossary doubles as an index. Second, the phase-gate timeline — illustrative package durations from raw land to a live cluster, with criticality calculated from Chapter 2.1’s dependency network, because a common scoping error is treating parallelizable work as serial and serial work as parallelizable. Third, the learning and community map — the certifications, conferences, and feeds that let a practitioner keep this material current after the ink dries.
None of it is meant to be read front-to-back; it is a lookup layer, and the tables are dense on purpose.
Glossary — efficiency, utilization & thermal metrics
The vocabulary is split across four thematic tables so each stays scannable. This first table covers the facility-efficiency and workload-utilization ratios; the canonical definitions and the post-PUE metric stack are built out in Chapter 15.1, with the utilization metrics anchored in Chapter 0.3 and the goodput reframing in Chapter 12.2.
| Term | Definition | Canonical chapter |
|---|---|---|
| PUE — Power Usage Effectiveness | Total facility energy / IT energy over the same period and boundary. The theoretical ideal is 1.0; an operating-point power ratio is not annual PUE. Says nothing about IT-side efficiency. | 15.1 |
| WUE — Water Usage Effectiveness | WUE: liters of site water usage per kWh of IT energy on a named boundary. Distinguish withdrawal, discharge and consumptive loss. Where evaporative rejection lowers cooling electricity, lower PUE comes with higher site WUE. | 15.1, 15.4 |
| ERF — Energy Reuse Factor | Fraction of facility energy exported as useful heat (district heating, etc.); higher is better (unlike the facility ratios PUE/WUE/CUE). | 15.1, 15.5 |
| REF / CUE — Renewable Energy / Carbon Usage | REF: renewable share of supply. CUE: kg CO2e per kWh of IT energy. The carbon companions to PUE. | 15.1, 15.3 |
| ITUE / TUE — IT / Total Usage Effectiveness | ITUE pushes the boundary inside the server (fans, VRMs, PSUs); TUE = PUE x ITUE, the true facility-to-transistor ratio. | 15.1 |
| MFU — Model FLOPs Utilization | Useful model FLOPs / matching dense peak over the same training window. Name model, precision and FLOP convention; exposed collectives and stragglers reduce the result. | 0.3, 13.9 |
| MBU — Model Bandwidth Utilization | Achieved memory bandwidth / peak, for memory-bound decode inference. The MFU analog when the bottleneck is HBM bandwidth, not FLOPs. | 0.3, 10.11 |
| Goodput | Useful work delivered per unit time after subtracting failed/restarted/stale work. The metric that matters; distinct from raw throughput and from facility availability. | 12.2, 10.11 |
| ETTR — Effective Training Time Ratio | Productive training wall-clock / total elapsed wall-clock. Folds in interruptions, checkpoint overhead, and restart loss; the goodput metric for training. | 12.2, 9.4 |
| Tokens-per-joule | Inference tokens delivered per joule at a named energy boundary. Cross-vendor comparisons require matched model, quality, precision, context, concurrency and latency SLO. | 15.1, 7.10 |
| $/GPU-hr | Cost or price per stated GPU-hour: installed, available, productive or billable. For build-vs-rent, align capex, power, cooling, staff, networking and finance scope before comparing. | 1.8, 7.11 |
| $/M-tokens | Cost or selling price per million tokens; keep the two separate. Specify input/output tokens, model quality and serving SLO before testing inference revenue against cost. | 1.8, 10.11 |
| EDP — Energy-Delay Product (per op) | Energy x latency, penalizing slow-and-power-hungry designs; a silicon/architecture figure of merit that resists gaming by either axis alone. | 7.10 |
| Delta-T (coolant rise) | Outlet minus inlet temperature of the same fluid: Q = mass flow × cp × ΔT. A 10 K coolant rise is a chosen design point, not exchanger approach; qualify it against the product envelope. | 5.1, 5.4 |
| Approach temperature | The temperature difference between two different streams at a defined terminal of a heat exchanger — at a CDU, facility supply against technology supply. It sizes the exchanger and sets how cold the technology loop can run; a CDU can carry a 10 K rise and a 3 K approach at the same time. | 5.11, 5.6 |
| NTU / effectiveness | Number-of-transfer-units and heat-exchanger effectiveness; the sizing math for CDUs and dry/wet coolers. | 5.1 |
| CFADS | Cash flow available for debt service under the named agreement: reconcile cash opex, taxes, maintenance, working capital and reserve movements. | 2.5 |
| DSCR | CFADS ÷ included interest and scheduled principal for the same period; specify the covenant and measurement period. | 2.5 |
Glossary — compute, memory & packaging
The silicon and packaging vocabulary that gates supply and density. The accelerator landscape lives in Chapter 7.1, HBM as the binding constraint in Chapter 7.6, and advanced packaging in Chapter 7.7.
| Term | Definition | Canonical chapter |
|---|---|---|
| HBM — High-Bandwidth Memory | Stacked DRAM (HBM3E/HBM4) integrated with the accelerator package. Capacity and bandwidth constrain different workloads; the named memory and packaging supply chain can gate delivery. | 7.6 |
| CoWoS — Chip-on-Wafer-on-Substrate | TSMC’s 2.5D packaging family integrates logic and HBM through variant-specific interposer/RDL structures. CoWoS capacity can gate assembly; identify the variant before applying a limit. | 7.7 |
| Interposer | The silicon (or organic/RDL) layer carrying high-density interconnect between logic and HBM in a 2.5D package; reticle-size limits drive the move to larger and stitched interposers. | 7.7 |
| XPU | Generic term for a non-GPU AI accelerator (TPU, Trainium/Inferentia, Maia, MTIA); hyperscaler custom silicon competing with merchant GPUs. | 7.4, 7.5 |
| MoE — Mixture of Experts | Sparse architecture activating a subset of expert sub-networks per token; widens expert-parallelism and reshapes both training fabric and inference KV-cache pressure. | 1.2, 8.5 |
| KV cache | Cached key/value tensors for attention during decode; its size scales with context length and concurrency, dominating inference memory and driving disaggregation. | 9.7, 10.11 |
| Quantization (FP8/FP4/INT8) | Reduced numerical precision to cut memory and lift throughput; the compute-vs-accuracy lever, increasingly native in Blackwell/Rubin-class silicon. | 7.10 |
| TDP — Thermal Design Power | Vendor-defined thermal design power for the named package or rack. It informs cooling duty; it is not automatically measured demand, electrical peak or facility provisioning power. | 5.1, 7.12 |
| Power transient / load step | Synchronized GPU draw swings (idle-to-full across thousands of GPUs in milliseconds) that stress the power chain; mitigated chip→BBU→BESS. | 4.5, 7.12 |
| SST — Solid-State Transformer | Power-electronics conversion with topology-specific isolation for MV-to-DC and 800 VDC racks. Compare full-system efficiency at the named duty, plus protection and serviceability. | 4.4, 4.7 |
| PVF | Program Vulnerability Factor: workload-dependent exposure of output to hardware faults, under the study’s fault model and coverage. | 14.3 |
Glossary — interconnect, fabric & networking
The two-tier network vocabulary: scale-up (inside the coherent domain) versus scale-out (across the cluster). Scale-up interconnect is treated in Chapter 8.2, scale-out topology and oversubscription in Chapter 8.5, scale-out protocols and transport in Chapter 8.4, and congestion control in Chapter 8.6.
| Term | Definition | Canonical chapter |
|---|---|---|
| NVLink domain (scale-up domain) | The set of GPUs sharing a coherent high-bandwidth NVLink/NVSwitch fabric (8 in HGX, 72 in NVL72, 576 in Rubin Ultra); its size sets tensor/expert-parallel ceilings. | 8.2, 8.5 |
| NVSwitch | NVIDIA's switch ASIC that fully connects a scale-up domain; NVLink-SHARP performs in-network reduction to accelerate collectives. | 8.2 |
| UALink | UALink is a multi-vendor scale-up alternative to NVLink; 200G 1.0 supports up to 1,024 accelerators. AMD Helios names UALoE; Ethernet transport is implementation-specific, not inherent to UALink. | 8.2 |
| InfiniBand (IB) | Low-latency lossless scale-out fabric with native RDMA and adaptive routing; the historical default for non-blocking training back-ends. | 8.4 |
| RoCE — RDMA over Converged Ethernet | RDMA carried on Ethernet (typically lossless via PFC/ECN+DCQCN); the open, cost-driven scale-out alternative to InfiniBand. | 8.4 |
| Spectrum-X | NVIDIA's Ethernet-based scale-out platform tuning RoCE for AI collectives (adaptive routing, congestion control); the Ethernet answer to InfiniBand. | 8.4 |
| UEC — Ultra Ethernet Consortium / UET | UEC issues Ultra Ethernet Transport: packet spray/reorder, UCCM congestion control and packet trimming. Select the dated transport revision in Appendix A and qualify the purchased AI/HPC stack. | 8.4, 8.6 |
| Rail-optimized / fat-tree | Rail alignment places corresponding GPU NICs on matching rails; a fat-tree is a switching topology. Leaf/spine counts and placement decide capacity; neither label guarantees collision-free collectives. | 8.5 |
| Oversubscription ratio | Downstream/upstream bandwidth at a named tier or cut: 1:1 is balanced, 3:1 has three units downstream per unit upstream. Failure state and workload traffic decide acceptable blocking and cost. | 8.5 |
| Bisection bandwidth | Minimum aggregate link capacity across an equal-half endpoint cut, with direction and failure state stated. It bounds all-reduce traffic; it is not measured collective throughput. | 8.5 |
| PFC / ECN / DCQCN | Lossless-Ethernet congestion-control mechanics: Priority Flow Control (pause), Explicit Congestion Notification, and the DCQCN tuning loop; mis-tuned, they cause head-of-line blocking and victim flows. | 8.6 |
| CPO — Co-Packaged Optics | Optical engines beside a switch/compute ASIC shorten electrical reach. For NVLink/scale-up or scale-out, trade power and reach against fault isolation, replaceable unit and repair logistics. | 8.10, 8.9 |
| NVMe-oF | NVMe over Fabrics (RoCE or TCP transport) for disaggregated storage; the placement-vs-transport tradeoff for the storage rail. | 8.5, 9.1 |
Glossary — facility, power, cooling & program
The building, electrical, mechanical, and project-management terms. Power topology lives in Chapter 4.1, DLC in Chapter 5.4, the reliability rethink in Chapter 12.2, and the integrated master schedule and critical path in Chapter 2.1.
| Term | Definition | Canonical chapter |
|---|---|---|
| SU — Scalable Unit (reference design) | The repeatable build block (a defined MW + GPU + cooling + fabric increment) that the capacity ramp is composed of; the unit of design reuse and procurement. | 1.7 |
| DLC — Direct-to-Chip Liquid Cooling | Cold plates on hot components fed by a CDU-isolated technology loop; select DLC where the named equipment heat split, airflow limits, density roadmap, and facility envelope require it. A water-fed rear door can bridge some air-side cases, subject to the named rack-and-door rating. | 5.4 |
| CDU — Coolant Distribution Unit | Coolant-distribution assembly with specified pumps, control and interfaces. A liquid-to-liquid CDU isolates FWS from TCS through an exchanger; valves, sensors and topology determine leak isolation. | 5.6, 5.13 |
| RDHx — Rear-Door Heat Exchanger | Water-fed liquid-to-air door sized to the named door/rack rating and operating envelope. Its coil connects to chilled or tempered water at the door; AALC/L2A is the room-air-rejecting brownfield step before full DLC. | 5.3, 5.10 |
| 800 VDC | Direct-current rack/distribution architecture for megawatt-class racks (NVIDIA/OCP Mt Diablo); cuts conversion stages and copper for ~600 kW–1 MW racks. | 4.7 |
| BBU / BESS | Battery Backup Unit (rack-level ride-through) and Battery Energy Storage System (facility-level); the chip→BBU→BESS spine that absorbs GPU load transients and bridges to gensets. | 4.5, 4.7 |
| Tier (Uptime I–IV) | Uptime Institute topology classification: Tier I (basic) → Tier IV (fault-tolerant). Tier III is concurrently maintainable; use the classification only after capacity, maintenance, and fault outcomes are fixed. | 12.1, 12.2 |
| 2N / N+1 | Capacity notation: N+1 adds one component beyond N; 2N provides two N-capacity systems. Maintenance continuity and fault survival depend on paths, controls and tested states, not the count alone. | 12.2 |
| RBD / Markov / Monte-Carlo | The three availability-modeling techniques: Reliability Block Diagrams, Markov state models, and stochastic simulation; the quantitative machinery behind the nines. | 12.5 |
| Phase gate (stage gate) | A go/no-go decision point between project phases where deliverables are reviewed and capital is released; the spine of the timeline table below. | 2.1 |
| IMS / critical path | Integrated Master Schedule and its critical path: the longest dependent chain of tasks whose slip slips the whole project; everything off it has float. | 2.1 |
| Long-lead equipment | Items whose procurement lead time (transformers, switchgear, chillers, GPUs) drives the schedule; ordered against a frozen design basis before they bottleneck go-live. | 2.3, 2.1 |
| Commissioning (Cx) L1–L5 | The five commissioning levels from factory acceptance (L1) through component, system, and integrated systems testing (L5 IST); proves the facility before load. | 13.1, 13.6 |
| Speed-to-power | The time from contract to energized MW; the binding constraint of the 2026 era and the primary siting screen. | 3.2 |
| TTFT / TPOT | Time-To-First-Token and Time-Per-Output-Token; the two latency SLOs that govern online-inference fleet sizing. | 10.11 |
| RPN | Ordinal FMEA priority S × O × D; not a failure probability. Review high severity separately. | F |
| UQD | Universal Quick Disconnect; qualify revision, size, materials, fluid and mating pair. Dripless describes rated conditions, not zero release in every state. | 5.13 |
| FWS / TCS | Facility Water System / Technology Cooling System; name the exchanger and all four supply/return measurement points. | 5.11 |
The project phase-gate timeline & critical path
A greenfield AI campus’s land-to-live schedule is the longest connected path through utility service, permits, equipment, construction and cluster acceptance. Firm megawatts often govern, but the dependency network must demonstrate it. The table below sequences the program as phase gates: each package’s illustrative duration, the gate decision that releases the next phase, and which dependency could make it critical; the last column identifies candidate gates, not calculated float. A zero-float path moves the finish one-for-one until another path controls. On a power-bound build the critical path runs through interconnection, not construction. The grid study, the utility agreement, and the substation/transformer lead time routinely dominate everything that follows, which is why land and power are secured before design is frozen and why long-lead electrical gear is ordered the moment the design basis is signed.
Read the duration ranges as one illustrative 2026 planning scenario for a >50 MW build — not survey medians and not commitments; rebuild them from your serving utility's milestone dates and current equipment quotes. A retrofit or colocation fit-out can reuse land, permits and construction only where those assets and permissions cover the new load. A contested interconnection or transformer queue can still control go-live; carry each surviving obligation into the network.
| Phase | Illustrative allowance | Gate decision (what releases the next phase) | Candidate dependency |
|---|---|---|---|
| 0. Scope & site search | 2–6 months | Workload profile, capacity ramp, and design basis signed; target market and shortlist approved. | Defines the released scope |
| 1. Land control | 1–4 months | Site optioned/acquired; zoning and entitlement path confirmed; environmental Phase I clear. | Controls site-specific starts |
| 2. Power / interconnection | 12–48 months | Executed interconnection agreement and firm-capacity / energization date; can bind when the utility service path controls the linked schedule. | Utility date can bind |
| 3. Permitting & entitlement | 6–18 months | Building, environmental, water, and air permits issued; often overlaps power but can become the binding gate. | Permit release can bind |
| 4. Design (concept → DD → IFC) | 6–12 months | Issued-for-construction documents; design basis frozen so long-lead gear can be ordered. | Package freeze gates orders |
| 5. Long-lead procurement | Equipment-specific; current quote required (parallel) | POs placed against frozen design; transformers/switchgear/chillers ordered early to de-risk the schedule. | Delivery can bind installation |
| 6. Construction (shell + fit-out) | 12–24 months | Substantial completion; building, electrical, and mechanical infrastructure ready for commissioning. | Readiness gates integration |
| 7. Commissioning (L1–L5 IST) | 3–9 months | Integrated Systems Testing (L5) passed; facility proven under simulated and staged real load. | Accepted plant gates live IT |
| 8. Cluster bring-up & burn-in | 1–4 months | GPU node burn-in, fabric validation, and reference-training/benchmark acceptance complete. | Accepted cluster gates service |
| 9. Staged ramp & go-live | 1–3 months | Staged power/load ramp to full; handover to operations; SLA clock starts. | Contractual end milestone |
The owner must decide whether expediting the transformer can still protect the customer date. The base network finishes in week 60. With the building ready in week 47, dock remains 40 + 4 = 44; installation finishes max(44, 47) + 6 = 53, and facility acceptance finishes max(44, 53) + 4 = 57. Racking finishes max(46, 47) + 2 = 49. Productive readiness is max(57, 49) + 6 = week 63, one week beyond the assumed deadline. Earlier transformer delivery buys no recovery while the building governs installation.
Assign the construction lead a week-46 building-release milestone: then installation/acceptance finish in weeks 52/56, racking in week 48, and productive readiness in week 62, flipping the deadline decision. At week 44 or earlier the dock path governs again and finish stays week 60. Record predecessor evidence before promising either date; energization alone does not finish acceptance or workload validation. Chapter 2.1 owns the network and probabilistic method; GAO’s Schedule Assessment Guide supplies the scheduling evidence discipline.
Learning & community map — certifications
Certifications split by discipline, and there is no single credential for an AI-data-center engineer — strong teams hold a spread across facility design, operations, and the network/compute stack. The table flags each credential, its issuer, and the role it maps to. Use it as a hiring and development reference, not a gate; deployed expertise in this field still outruns any certificate.
| Credential | Issuer | Maps to role / domain |
|---|---|---|
| ATD — Accredited Tier Designer | Uptime Institute | Facility design engineers / licensed PEs; the only credential mapping directly to the Tier classification used in commissioning. |
| ATS — Accredited Tier Specialist | Uptime Institute | Operations and facility staff managing/maintaining to Tier criteria; the operations companion to the ATD. |
| CDCDP — Certified Data Centre Design Professional | CNet Training (BTEC-accredited) | Multidisciplinary facility-design competency; the design rung of the CNet ladder. |
| DCDC — Data Center Design Consultant | BICSI | BICSI's design credential, examined against ANSI/BICSI 002; separate issuer, eligibility, and curriculum from CNet's CDCDP. |
| CDCMP / CDCEP | CNet Training | Data Centre Management / Energy Professional; operations leadership and efficiency engineering. |
| CDCP / CDCS / CDCE | EPI | Certified Data Centre Professional → Specialist → Expert; a tiered facility-operations ladder. |
| PE (Electrical / Mechanical) | State licensing boards (US) / equivalents | The statutory license to stamp design documents; foundational for Phase 4 sign-off. |
| NVIDIA-Certified (NCP/NCA, networking & AI infra) | NVIDIA | GPU-cluster and fabric engineers; CUDA/NCCL, InfiniBand/Spectrum-X, and DGX/SuperPOD operations. |
| Vendor network tracks: Cisco CCNP; Arista ACE; Juniper JNCIP | Cisco / Arista / Juniper | Scale-out fabric engineers building and tuning RoCE/lossless-Ethernet AI back-ends. |
| OCP-aligned training | Open Compute Project community | Open-hardware rack/power/cooling literacy (Open Rack, Mt Diablo 800 VDC, ORW). |
Learning & community map — conferences & feeds
Two final tables. The conference calendar is the place to calibrate against the field — hardware roadmaps break at OCP and GTC, facility practice at DCD and 7x24, network practice at the OCP networking tracks and vendor summits. The feeds help locate changes between editions; verify quantitative decisions against primary evidence: independent analysis (SemiAnalysis), facility-industry reporting (DCD, Data Center Frontier), the standards bodies themselves, and the operator engineering blogs that publish primary reports from named production fleets.
| Event | Cadence / dated edition and issuer program | Why it is on the calendar |
|---|---|---|
| OCP Global Summit | Annual Global Summit; 2026: October 12–15, San Jose. Check later editions separately. | Where hyperscaler-grade open hardware breaks: Open Rack, 800 VDC / Mt Diablo, cooling and networking working groups. |
| NVIDIA GTC | Annual main GTC; 2027: March 15–18, San Jose. Regional GTCs have separate programs. | The accelerator/roadmap keynote that sets the density-ramp expectations the rest of the industry designs against. |
| DCD>Connect (regional series) | Multiple editions: NYC, London, Virginia, APAC; Official program; select the event year before booking | The facility-operator and capital-markets gathering; siting, power, cooling, and build-out practice. |
| 7x24 Exchange | US spring and fall conferences; fall 2026: October 25–28, San Antonio. | Mission-critical facility operations, commissioning, and reliability — the Cx/operations community. |
| Datacloud / Data Centre World | Annual, separate series: Datacloud: June 2–4, 2027, Cannes; Data Centre World London: March 10–11, 2027; other DCW editions have separate programs. | European and global colocation, investment, and infrastructure deal-making and design practice. |
| DesignCon | Annual; February 2–4, 2027, Santa Clara. | Signal/power integrity and high-speed interconnect engineering — the physical-layer fabric community. |
| Hot Chips / ISSCC / SC | Annual academic/industry programs, separately organized: Hot Chips, ISSCC and SC26. | Silicon architecture (Hot Chips, ISSCC) and HPC/AI supercomputing (SC) — the upstream compute and packaging research. |
| Source | Type | What it is good for |
|---|---|---|
| SemiAnalysis | Independent analysis (paid) | Analyst $/GPU-hr models, CoWoS/HBM supply-chain work, rack teardowns and fabric economics; inspect the method and obtain supplier evidence for procurement. |
| Data Center Dynamics (DCD) | Industry news | Facility builds, power deals, interconnection news, and roadmap reporting across the global market. |
| Data Center Frontier | Industry news | US-focused facility engineering, power-architecture, and cooling-transition reporting. |
| The Next Platform / The Register (on-prem) | Technical journalism | Systems-level AI-infrastructure and interconnect analysis with an engineering bent. |
| LBNL (Berkeley Lab) — Queued Up et al. | Primary research | Authoritative interconnection-queue, grid, and data-center energy studies — the source behind the power figures. |
| Uptime Institute (research & blog) | Standards / research | Tier standards, outage analyses and the annual data-center survey; retain the surveyed population, definitions and limitations. |
| OCP / UEC / UALink / OIF (standards bodies) | Primary specs | The authoritative spec text for open rack/power/cooling and AI-fabric standards — read the spec, not the summary. |
| Operator engineering blogs (Meta, Microsoft, Google) | Operator primary reports | RoCE-at-scale, checkpointing, fleet-reliability, and cooling practice published from real production clusters. |
How to keep this appendix from going stale
Every figure in this guide has a half-life. Density numbers move each accelerator generation; interconnection-queue medians move each ISO filing; lead times move with the transformer market. Keeping a reference like this useful takes the same habit that keeps the guide current: cite the source and the as-of date for every load-bearing number, and re-check the ones that gate a decision before you act on them. The feeds table is the maintenance plan. When this guide and a primary source disagree, the primary source wins — and the glossary entry's canonical chapter is where you go to understand why the number moved, not just that it did.
Read the four layers together: the glossary tells you what a term means, the canonical chapter why it matters, the phase-gate timeline when the decision is due, and the community map where to check that the answer still holds. Apart, each ages; together, they keep the reference honest a year after it ships.
Cite this chapter
Fehn, J. (2026). Glossary, Phase-Gate Timeline & Learning/Community Map (Chapter E). The Definitive Guide to AI Data Centers. https://aidatacenterguide.com/appendix-appendices-and-reference-data/e-glossary-phase-gate-timeline-and-learning-community-map (accessed 2026-09-29).
@misc{aidc-E,
author = {Fehn, Jacob},
title = {Glossary, Phase-Gate Timeline & Learning/Community Map (Chapter E)},
howpublished = {The Definitive Guide to AI Data Centers},
year = {2026},
url = {https://aidatacenterguide.com/appendix-appendices-and-reference-data/e-glossary-phase-gate-timeline-and-learning-community-map},
note = {Accessed 2026-09-29}
}