The DC Power Revolution: 48V → ±400V → 800V & Disaggregated Sidecar Power

The data-center power chain used to be an argument about efficiency at the margin: a percentage point of UPS loss here, a transformer K-factor derate there. The AI rack ended that argument by changing the units. A 40 kW H100 rack draws a few hundred amps on a 48 V in-rack bus; a 132 kW GB200 NVL72 draws ~2,800 A; a ~600 kW Kyber-class rack on the 2027 roadmap draws over 12,000 A if you keep the bus at 48 V. There is no busbar, no connector, and no blind-mate interface that carries 12 kA inside a rack without the copper itself becoming the dominant cost, the dominant mass, and the dominant heat source. The current ran into a wall, and the DC power revolution is the industry's response to it.

This chapter treats the revolution as a sequence of decisions: whether to raise the bus voltage at all (and the threshold below which you should not), which DC voltage to standardize on (±400 V vs 800 V, and why the answer is a supply-chain decision as much as a physics one), where the conversion lives (inside the IT rack vs a disaggregated sidecar), and how you collapse the conversion chain (the solid-state-transformer path to a single MV→DC stage). We close on the genuinely new engineering — protecting and grounding a high-voltage DC bus that has no current zero-crossing to help the breaker — and on the unglamorous truth that for a large share of 2026 inference halls, AC still wins. The protection and grounding details have a canonical home in Chapter 4.11; the SST itself is engineered in Chapter 4.4; here we make the architectural decisions that decide whether you ever reach for them.

Start from the one equation that governs everything downstream. For a fixed power P delivered at voltage V, the current is I = P/V, and the resistive loss in the conductor is I²R. Loss scales with the square of current, so it scales with the inverse square of voltage. Raise the distribution voltage by 8x and, for the same delivered power, current drops 8x and conductor loss drops 64x — or, equivalently, you carry the same power through a fraction of the copper. NVIDIA's framing of its 800 VDC reference is exactly this: 800 VDC moves over 150% more power through the same copper cross-section than a 54 VDC rack bus (NVIDIA, 2025–26). It is the reason the rack roadmap forces the voltage up.

The copper wall arrives as a step function, not a gradual slope. Below roughly 100 kW/rack, a 48 V in-rack bus is comfortable. From ~100 kW to ~200 kW it gets expensive and hot but remains buildable with heavier busbars and more blind-mate contacts. Past ~200 kW the busbar cross-section, the connector contact resistance, and the sheer mass of copper make the conventional rack bus untenable — and that is precisely the band the Rubin/Kyber generation pushes through. So the first fork is binary: does your rack roadmap cross ~200 kW within the depreciation life of the building you are scoping? If yes, you are committing to a high-voltage DC bus and everything below applies. If no, you are over-engineering, and the cleaner decision is to stay on AC distribution to the rack and revisit at the next refresh. → density wall in Chapter 5.1; the rack-power roadmap in Chapter 4.1.

Once you have decided to raise the bus, the substantive fork is which voltage — and in 2025–26 the industry split into two camps that are converging on a shared answer but arrived from opposite directions. The split is the single most important architectural decision in this chapter.

±400 VDC (bipolar) — the supply-chain decision. Google, Meta, and Microsoft co-authored the OCP Mt. Diablo / Diablo 400 specification around a bipolar ±400 V bus: two rails at +400 V and −400 V about a grounded midpoint, giving an 800 V rail-to-rail span while keeping each conductor only 400 V from ground. The reason is not primarily electrical — it is procurement. The electric-vehicle industry built a mature, high-volume supply chain at the 400 V class: 650 V GaN FETs, 400 V-class film capacitors, automotive connectors, fuses, and contactors are all in volume production and second-sourced. Standardizing the rail at 400 V lets the data-center industry ride the EV supply chain rather than build a new high-voltage component ecosystem from scratch. Google said exactly this at OCP EMEA 2025: 400 VDC 'allows us to leverage the supply chain established by electric vehicles.' The consequence you accept is a bipolar topology — two rails, a midpoint to ground and monitor, and the balancing question that comes with it.

800 VDC (nominal) — the single-step decision. NVIDIA's 800 VDC reference architecture for the 1 MW Kyber-class rack targets a unipolar 800 V bus delivered, ideally, straight from medium voltage through one conversion. The case is that 800 V at the rail minimizes current and copper for the largest racks and aligns the whole facility on one number from the solid-state transformer to the rack inlet. The consequence is that 800 V is above the comfortable ceiling of the EV-grade 400 V-class component pool: you move to 1,200 V-class SiC devices and connectors/breakers rated for a continuous 800 V DC bus, a thinner and more expensive component market in 2026. In practice the two camps reconcile cleanly — a bipolar ±400 V distribution is an 800 V rail-to-rail system — and the ecosystem (Eaton, ABB, Schneider, Vertiv, Siemens, Delta) is building to a common '800 V-class' target with bipolar ±400 V as the dominant physical implementation. → the SST that feeds either bus in Chapter 4.4.

The second architectural decision is orthogonal to voltage and at least as consequential: where does the AC→DC conversion physically live? The conventional answer is 'in the IT rack' — power shelves of rectifiers occupying rack units that could otherwise hold compute, and a power-supply refresh chained to the compute refresh. The disaggregated answer, embodied in Mt. Diablo, is to pull all the rectification out of the IT rack and into a dedicated sidecar power rack standing beside the compute racks in the same row. The sidecar is full of power shelves; it converts facility AC to the high-voltage DC bus and feeds one or more adjacent IT racks over a DC busbar or a set of HVDC cables (Diablo's later revisions move to 16x 50 kW ±400 V cables in place of horizontal busbars).

Name the consequence, because it is the whole point. Disaggregation decouples the power-conversion lifecycle from the compute lifecycle. Rectifiers and DC-DC stages are long-lived, slow-moving, and improve incrementally; accelerators churn on a ~2-year cadence and consume every rack unit you can give them. When conversion lives in the IT rack, every compute refresh either strands working power hardware or forces a power redesign. When it lives in the sidecar, you refresh compute racks against an unchanged power spine, and you reclaim the rack units the power shelves used to occupy for more compute. The cost you accept is a row-level architecture: the sidecar consumes floor area and aisle space, the DC interconnect between sidecar and IT rack becomes a new failure domain and a new connector-standardization problem, and your redundancy now has to be reasoned about at the sidecar-feeds-N-racks level rather than per rack. → busway/PDU baseline and the ORv3 48 V bus this extends in Chapter 4.6; rack BBU placement in Chapter 4.5.

The third decision is how many conversion stages stand between the medium-voltage feeder and the DC bus. The legacy AC chain is a stack of conversions — MV→LV transformer, then a UPS that rectifies AC to DC for the battery and inverts back to AC, then PDU distribution, then in-rack AC→48 V, then 48 V→point-of-load — and each stage costs efficiency, copper, heat, and a maintainable box. End-to-end, the legacy AC chain lands somewhere between ~61% and ~87.5% utility-to-VRM depending on vintage (SemiAnalysis, 2025). The DC architecture's promise is to strip the redundant AC↔DC round-trips and clear >92% end-to-end.

The most aggressive version of that promise is the solid-state transformer: a power-electronic stage that takes medium voltage directly to 800 VDC in essentially one conversion, replacing the LV transformer and the rectifier front-end at once. ETH Zurich's INTELEC 2025 prototype demonstrated 98.1% efficiency converting 13.2 kVAC to 800 VDC at 400 kW — a credible single-stage MV→DC at data-center scale. The fork here is timing, not principle. The SST is the right long-run topology, but in 2026 it is early: vendors are racing toward UL listing (DG Matrix, the only SST in NVIDIA's MGX reference, targeted UL certification around Q2 2026; Amperesand, Heron Power, and others claim ~98.5% but at sub-MW prototype scale), and the field has not yet shown a 3–6 MW-class unit sustaining >99% under continuous load. So the decision is: take the single-stage SST now and accept first-mover risk on a not-yet-listed component, or stage it — deploy conventional MV→LV→rectifier feeding the DC bus today, and swap in the SST when it is listed and field-proven, having designed the DC bus interface to accept either. The canonical SST engineering treatment lives in Chapter 4.4.

If the conversion is the easy part, the protection is the hard part — because direct current behaves nothing like alternating current at a fault, and most of the installed protection wisdom assumes AC. This is where the DC decision stops being a spreadsheet and becomes a safety case.

No zero-crossing. An AC arc self-extinguishes 100–120 times a second when the current passes through zero; a mechanical breaker exploits that to interrupt the fault. A DC fault current has no zero-crossing — the arc wants to sustain itself indefinitely — so an 800 V DC fault is far harder to clear and far more dangerous than a 480 V AC one. The answer is the solid-state circuit breaker (SSCB): a semiconductor-based interrupter (SiC-based) that opens in microseconds, before fault energy accumulates, often paired with a fast mechanical disconnect for galvanic isolation. SSCBs are a different device class with different coordination behavior than the molded-case breakers AC designers know, and the protection-coordination study has to be redone in the DC domain.

Arc-flash and touch safety. A sustained DC arc carries more incident energy than the equivalent AC event, so arc-flash analysis and PPE boundaries must be recomputed for the DC bus, and the bipolar ±400 V design is partly a touch-safety choice — keeping each conductor 400 V from ground rather than 800 V. Grounding and isolation are where ±400 V and 800 V genuinely diverge: a bipolar ±400 V bus references a grounded midpoint and must be balanced and monitored, while a unipolar or deliberately ungrounded (IT-style) 800 V bus survives a first ground fault but demands continuous insulation/ground-fault monitoring to catch that first fault before a second one makes a short. This — the DC-bus grounding and ground-fault-monitoring problem on ungrounded ±400/800 V systems — is the novel piece, and it has its canonical engineering home in Chapter 4.11. Treat this section as the architectural flag: choosing a DC bus means inheriting a DC protection and grounding program you do not yet have staff trained for.

The honest conclusion of this chapter is that the DC revolution is real and inevitable at the top of the density range — and irrelevant to a large share of the 2026 fleet. The migration is a coexistence problem, not a flag day. Most operators will run mixed estates: AC busway feeding 48 V racks for the inference and general-compute halls, and DC distribution (±400 V or 800 V, via sidecar) reserved for the densest training/Kyber-class rows. The two architectures share a facility, a substation, and an MV distribution, and diverge only in the last conversion stages — which is exactly why the sidecar/SST decisions are made at the row level, not the building level.

AC still wins, decisively, when: rack density stays below ~200 kW (the threshold where copper does not yet force the issue); the workload is latency-bound inference where the binding constraints are uptime and geo-distribution, not rack copper; the build is a retrofit of an AC-distributed hall where ripping to DC strands working switchgear and PDUs; the operator lacks the DC protection/grounding competency and cannot staff it on the project timeline; or the schedule cannot absorb the thinner DC vendor pool and pending listings. DC wins when the rack roadmap is committed to crossing ~200 kW within the building's life, the workload is training-shaped and density-first, and the operator is building greenfield with the engineering depth to take on the new protection regime. The fork, as always, is set by the workload archetype and the density ramp — not by the elegance of the power architecture. → workload-driven scoping in Chapter 1.1; the density wall that triggers all of this in Chapter 5.1.