The DC Power Revolution: 48V → ±400V → 800V & Disaggregated Sidecar Power

The data-center power chain used to be an argument about efficiency at the margin: a percentage point of UPS loss here, a transformer K-factor derate there. The AI rack ended that argument by changing the units. A 40 kW H100 rack draws roughly 830 A on a 48 V in-rack bus; a 132 kW GB200 NVL72 draws ~2,800 A and a GB300 NVL72 at its up-to-142 kW facility basis about 2,950 A; a VR200 NVL72 at 188 kW Max Q / 228 kW Max P draws about 3,900–4,750 A; a ~600 kW Kyber-class rack on the 2027 roadmap draws over 12,000 A if you keep the bus at 48 V. There is no busbar, no connector, and no blind-mate interface that carries 12 kA inside a rack without the copper itself becoming the dominant cost, the dominant mass, and the dominant heat source. Current, not voltage, is the constraint the DC power revolution exists to relieve.

The revolution unfolds as a chain of decisions. First, whether to raise the bus voltage at all — and the threshold below which you should not. Then which DC voltage to standardize on: ±400 V versus 800 V, a choice driven as much by supply chain as by physics. Then where the conversion lives — inside the IT rack or a disaggregated sidecar — and how far you collapse the conversion chain, down to the solid-state-transformer path that takes MV to DC in a single stage. The genuinely new engineering waits at the end: protecting and grounding a high-voltage DC bus that has no current zero-crossing to help the breaker — plus the unglamorous truth that for a large share of 2026 inference halls, AC still wins. Protection and grounding have their canonical home in Chapter 4.11; the SST itself is engineered in Chapter 4.4; here we make the architectural decisions that decide whether you ever reach for them.

Start from the one equation that governs everything downstream. For a fixed power P delivered at voltage V, the current is I = P/V, and the resistive loss in the conductor is I²R. Loss scales with the square of current, so it scales with the inverse square of voltage. Raise the distribution voltage by 8x and, for the same delivered power, current drops 8x and conductor loss drops 64x — or, equivalently, you carry the same power through a fraction of the copper. NVIDIA's framing of its 800 VDC reference is exactly this: its October 2025 article claims 157% more power through the same wire gauge — comparing a three-wire DC feed (POS/RTN/PE) against four-conductor 415 VAC — while its May 2025 article put the same shift at ~85% on a different conductor basis. Both are vendor comparisons on specific topologies, not constants; compute your own current and loss from the conductor count and route. The direction, though, is the physics above — and it is the reason the rack roadmap forces the voltage up.

The copper wall arrives as a step function, and in 2026 the step sits at roughly ~200 kW per rack — the load at which a conventional 48 V in-rack bus runs out of offered busbar current and thermal rating (an in-rack busbar boundary, not a cutoff on the rack’s AC input). Below roughly 100 kW/rack a 48 V bus is comfortable. From ~100 kW to ~200 kW it gets expensive and hot but remains buildable with heavier busbars and more blind-mate contacts. Past ~200 kW the busbar cross-section, the connector contact resistance and the sheer mass of copper make the conventional rack bus untenable unless the named rack’s approved configuration carries a higher busbar rating — and that is precisely the band the Rubin/Kyber generation pushes through. So the first fork is whether the rack roadmap exceeds the offered interface within the depreciation life of the building, including surviving-feed duty and service access. Beyond the offered bus rating, compare a qualified higher-current low-voltage interface with high-voltage DC; each carries a different insulation, thermal and service consequence. Flex's Vera Rubin NVL72 power shelf takes three-phase AC in and puts out 52 VDC at full load and 110 kW per shelf (Flex’s June 1, 2026 datasheet), and NVIDIA specifies 5 kA liquid-cooled rack busbars; neither is a whole-rack rating. Decide against the named rack's approved electrical configuration, its physical routing, losses, serviceability and availability. If the existing AC interface meets that load and failure envelope, retaining it can avoid stranded switchgear and PDUs; compare tendered losses and replacement costs before revisiting at the next refresh. → density wall in Chapter 5.1; the rack-power roadmap in Chapter 4.1.

Once you have decided to raise the bus, the substantive fork is the rail and grounding topology — and in 2025–26 the industry split into two camps that are converging on a shared answer but arrived from opposite directions. It is the chapter's central architectural fork.

Bipolar ±400 VDC — an 800 V rail-to-rail topology with a midpoint. Google, Meta, and Microsoft co-authored the OCP Mt. Diablo / Diablo 400 specification around a bipolar ±400 V bus: two rails at +400 V and −400 V about a grounded midpoint, giving an 800 V rail-to-rail span while the selected midpoint bond establishes nominal 400 V pole-to-earth references; an HRG first fault can shift those references. The reason is not primarily electrical — it is procurement. The electric-vehicle industry built a mature, high-volume supply chain at the 400 V class: 650 V GaN FETs, 400 V-class film capacitors, automotive connectors, fuses and contactors are component sourcing candidates; each still needs the actual continuous voltage, transients, fault interruption, creepage and service qualification, rather than inheriting installation approval from the EV label. Standardizing the rail at 400 V lets the data-center industry ride the EV supply chain rather than build a new high-voltage component ecosystem from scratch. Google said exactly this at OCP EMEA 2025: 400 VDC 'allows us to leverage the supply chain established by electric vehicles.' The consequence you accept is a bipolar topology — two rails, a midpoint to ground and monitor, and the balancing question that comes with it.

Unipolar nominal 800 VDC — a different rail/grounding topology at the same nominal rail-to-rail class. NVIDIA's 800 VDC reference architecture for the ~600 kW Kyber-class rack (roadmap headroom toward ~1 MW) targets a unipolar 800 V bus delivered, ideally, straight from medium voltage through one conversion. The case is that 800 V at the rail minimizes current and copper for the largest racks and aligns the whole facility on one number from the solid-state transformer to the rack inlet. The consequence is that 800 V is above the comfortable ceiling of the EV-grade 400 V-class component pool: 1,200 V-class SiC devices are one candidate, while the chosen switching topology determines device stress; connectors and breakers still need the actual continuous voltage, transients, fault duty and installation qualification. In practice the two camps reconcile cleanly — a bipolar ±400 V distribution is an 800 V rail-to-rail system — and the ecosystem (Eaton, ABB, Schneider, Vertiv, Siemens, Delta) is building to a common '800 V-class' target with bipolar ±400 V as the dominant physical implementation. In 2026 the convergence became explicit and published: Google, Microsoft, and NVIDIA co-authored an OCP LVDC white paper (Mar 2026) and the first Solid-State Transformer Specification (v0.3, Jul 2026), jointly describing 800 VDC as one open architecture with two coexisting deployment paths — an LVDC sidecar power rack converting existing 480 VAC locally (the Mt Diablo lineage; a "Mt Diablo 2.0" for native 800 V is forthcoming) as the fast path into today's AI factories, and direct MVAC→800 VDC via MW-scale transformer-rectifiers or SST skids as the endgame — with 80+ manufacturers building to the specs (OCP joint blog, 2026-08-11). NVIDIA's own product timeline matches: a hybrid MGX-compatible 800 VDC power rack in H2 2026, native 800 V with Kyber in 2027. → the SST that feeds either bus in Chapter 4.4.

The second architectural decision is orthogonal to voltage and at least as consequential: where does the AC→DC conversion physically live? The conventional answer is 'in the IT rack' — power shelves of rectifiers occupying rack units that could otherwise hold compute, and a power-supply refresh chained to the compute refresh. The disaggregated answer, embodied in Mt. Diablo, is to pull all the rectification out of the IT rack and into a dedicated sidecar power rack standing beside the compute racks in the same row. The sidecar is full of power shelves; it converts facility AC to the high-voltage DC bus and feeds one or more adjacent IT racks over a DC busbar or a set of HVDC cables (freeze the output count, connector, current and fault boundary from the offered Diablo revision; a reported 16 × 50 kW arrangement is not established by the opened v0.7.0 specification).

Disaggregation decouples the power-conversion lifecycle from the compute lifecycle. Rectifiers and DC-DC stages are long-lived, slow-moving, and improve incrementally; accelerators churn on a ~2-year cadence and consume every rack unit you can give them. When conversion lives in the IT rack, every compute refresh either strands working power hardware or forces a power redesign. When it lives in the sidecar, you can refresh compute racks against the existing power spine and reclaim the rack units formerly occupied by shelves, provided voltage, polarity, grounding, control and protection interfaces remain compatible. The cost is a row-level architecture: the sidecar consumes floor area and aisle space, the DC interconnect between sidecar and IT rack becomes a new failure domain and a new connector-standardization problem, and redundancy is now reasoned about at the sidecar-feeds-N-racks level, not per rack. → busway/PDU baseline and the ORv3 48 V bus this extends in Chapter 4.6; rack BBU placement in Chapter 4.5.

Compare direct MV-to-DC with transformer-plus-rectifier conversion using the common-boundary ledger in Chapter 4.1. Retain every downstream conversion and auxiliary load: an SST does not remove rack point-of-load conversion or automatically provide outage energy.

The procurement fork is concrete. ETH Zurich’s INTELEC 2025 keynote reports a 400 kW, 13.2 kVAC → 800 VDC industrial prototype at 98% efficiency (reported, not a primary test report), frames 98–98.5% as today’s state of the art and 99% as the next target; DG Matrix, Amperesand and Heron Power each claim ~98.5% for commercial units at pre-production scale, and no vendor had completed UL certification for a data-center SST as of May 2026 (SemiAnalysis, May 26, 2026) — DG Matrix’s June 17, 2026 announcement targeted UL certification by the end of Q2, and full 800 VDC code support is an NEC 2029 target. So the fork is timing, not principle: take the single-stage SST now and accept first-mover risk on a not-yet-listed component, or stage it. Carry the SST only when its certification evidence, MV protection, isolation, output grounding and service tests close with the delivery commitment. Otherwise retain conventional conversion and reserve a documented future interface; a later listed SST still needs compatibility qualification before it can replace that plant. Chapter 4.4 owns the converter qualification.

If the conversion is the easy part, the protection is the hard part — because direct current behaves nothing like alternating current at a fault, and most of the installed protection wisdom assumes AC. Protection, not conversion, is where a DC bus becomes a safety case rather than a spreadsheet line.

No zero-crossing. An AC fault current passes through zero 100–120 times a second, and a mechanical breaker exploits those zeros to interrupt the fault — an opportunity, not a guarantee, because the arc restrikes if dielectric recovery across the parting contacts is too slow. A DC fault current offers no such opportunity: the arc wants to sustain itself indefinitely, so interrupting it takes equipment that forces a current zero or absorbs the energy outright. Which of the two events is more dangerous at a given voltage is settled by an arc-flash study, not by the voltage number. One option is the solid-state circuit breaker (SSCB): a semiconductor interrupter, such as a qualified SiC design, that opens rapidly to limit additional source-fed fault energy, often paired with a mechanical disconnect for galvanic isolation. DC-rated fuses, electromechanical and hybrid devices are alternatives when their voltage, prospective-current and clearing characteristics meet the study. Charged capacitors contribute their stored energy regardless. SSCBs are a different device class with different coordination behavior than the molded-case breakers AC designers know, and the protection-coordination study has to be redone in the DC domain.

Arc-flash and touch safety. Incident energy on a DC bus is set by available fault current, arc behavior, clearing time, enclosure and working distance, and no AC study transfers across, so arc-flash analysis and PPE boundaries must be recomputed for the DC bus by a DC method, and an ideal solid midpoint on a bipolar ±400 V bus holds each conductor 400 V from earth in normal operation, whereas an end bond puts the opposite pole at 800 V. Study HRG and isolated outputs separately for first-fault current, healthy-pole stress, detection and clearing; the nominal reference alone does not establish touch safety. Grounding and isolation are where ±400 V and 800 V genuinely diverge: a bipolar ±400 V bus references a grounded midpoint and must be balanced and monitored, while first-fault behavior on a unipolar or deliberately ungrounded (IT-style) 800 V bus depends on the actual bond, isolation, capacitance, leakage and protective controls. Specify compatible continuous insulation/ground-fault monitoring and isolation to detect the first fault and execute the studied protective response before an opposite-pole fault creates a short. This — the DC-bus grounding and ground-fault-monitoring problem on ungrounded ±400/800 V systems — is the novel piece, and it has its canonical engineering home in Chapter 4.11. Treat this section as the architectural flag: choosing a DC bus means inheriting a DC protection and grounding program you do not yet have staff trained for.

Equal full-span voltage means equal ideal load current, not equal fault behavior. I = 200,000 W / 800 V = 250 A in either full-span connection. The isolated capacitor starts with E = ½CV² = ½ × 0.020 F × (800 V)² = 6.4 kJ. For the assumed passive path, V(t) = 800e^−t/(RC); reaching the project’s calculation endpoint takes 3,000 Ω × 0.020 F × ln(800/10) = about 260 s, inside 300 s. Initial resistor dissipation is 800²/3,000 ≈ 210 W and the discharge deposits almost 6.4 kJ: its pulse/continuous thermal rating needs separate qualification.

The capacitance crossover is 300/[3,000 × ln(80)] ≈ 23 mF; 23 mF does not pass the exact inequality. At 40 mF, discharge takes about 530 s and the 300 s access schedule fails; extend the interlocked wait or qualify a different discharge network. The project can retain the 20 mF candidate for this screen, but service release remains HOLD until all source isolation, discharge-path failure, voltage verification and interlock tests pass. A first earth fault changes rail-to-earth stress according to the actual bond; the capacitor calculation neither rates a breaker nor proves first-fault safety. Chapter 4.11 owns detector/earthing selection, and the rack supplier owns the Chapter 7.12/7.13 interface. No automotive component analogy substitutes for installed-system qualification.

The DC revolution is real and inevitable at the top of the density range, and irrelevant to a large share of the 2026 fleet. The migration is a coexistence problem, not a flag day. Most operators will run mixed estates: AC busway feeding 48 V racks wherever the deployed rack class stays inside the 48 V envelope, and DC distribution (±400 V or 800 V, via sidecar) reserved for the Kyber-class rows that do not. Rack kW and the approved rack configuration decide that, not whether the row is labelled training or inference — frontier inference deploys the same NVL72-class racks as training (Chapter 4.6). The two architectures share a facility, a substation, and an MV distribution, and diverge only in the last conversion stages — which is why the sidecar/SST decisions are made at the row level, not the building level.

AC still wins, decisively, when: the approved rack stays inside its AC current, thermal and failure envelope, below the copper wall; a latency-bound inference deployment can favor existing distributed capacity, but inference uses the same dense racks as training; the build is a retrofit of an AC-distributed hall where ripping to DC strands working switchgear and PDUs; the operator lacks the DC protection/grounding competency and cannot staff it on the project timeline; or the schedule cannot absorb the thinner DC vendor pool and pending listings. DC wins when the offered DC configuration resolves a demonstrated rack-current, routing or loss constraint within the building’s life, whether the dense workload is training or inference, and the operator is building greenfield with the engineering depth to take on the new protection regime. The named rack configuration and the density ramp decide the call; the elegance of the power architecture does not. → workload-driven scoping in Chapter 1.1; the density wall that triggers all of this in Chapter 5.1.