Custom ASICs & the Merchant-Silicon Disruption

The previous four chapters treated accelerators as products you select. Here silicon is something you can commission — and the only question worth asking first is whether the workload is big enough, durable enough, and stable enough to pay back a chip you must design, validate, and manufacture before it earns a cent. The merchant-GPU model (buy NVIDIA, inherit CUDA and the allocation queue) is the default because someone else paid the fixed cost. A custom ASIC inverts that bargain: you absorb the non-recurring engineering (NRE) and the lead time up front, in exchange for a chip tuned to your workload at a potentially lower cost per token after program costs, with only the programmability you designed in. What changed in the 2025–2026 era is that for the largest inference buyers the trade became a funded alternative requiring its own program case, and the merchant-silicon design houses (Broadcom, Marvell) turned chip design into a service you can buy.

The custom-silicon economics come first — NRE, lead time, minimum-volume thresholds, the breakeven against a merchant GPU — then the specialization-vs-programmability fork that determines whether the bet survives an architecture shift, and finally the hybrid fleet most large operators actually run. A custom ASIC is the highest-leverage and least-reversible procurement decision in Part 7. Clear the volume, software and delivery gates and you can earn a lower cost-per-token; miss them and you own a stranded mask set and a chip that lost to the next merchant generation before it shipped. → the XPU programs themselves live in Chapter 7.4; the merchant GPUs you are deciding against are in Chapter 7.2 and Chapter 7.3.

A custom ASIC has two cost components that a merchant GPU hides from you because they are already amortized across NVIDIA's millions of units: NRE (the one-time cost to design, verify, and tape out the chip) and per-unit recurring cost (wafer, HBM, packaging, test — the same supply chain the merchant GPU draws from). The whole case for building rests on a single inequality: does the matched useful-service cost advantage, multiplied by your committed volume, exceed the NRE plus software, sustaining and delay cost? Below that threshold the program never pays back; above it, every unit past breakeven is structural margin.

NRE is the number that disciplines the decision. At the leading edge the fixed cost of a new design has exploded: IBS estimated $590M to develop a mainstream 3 nm chip, versus $416M at 5 nm and $217M at 7 nm (Semiconductor Engineering, May 2021). Most of that is not the mask set — a leading-edge set passed $10M at 7 nm and heads toward ~$40M at 3 nm (SemiAnalysis, July 2022) — but the verification, validation, IP licensing, and physical-design labor that a leading-edge tape-out demands, and that labor is spent long before a shippable part exists. For a complete hyperscale accelerator program the reported figure is ~$500M for a single chip version, roughly doubling once the software and peripherals around it are built (Reuters, February 2025). A node-cost estimate or a mask-set price is therefore a floor, not a program budget: budget chip design, software, package qualification, sustaining and a delay reserve separately; the stated-assumption case below tests those obligations without inventing a supplier quote.

Then the lead time. From committed architecture to silicon in a rack, the development clock consumes the remaining commercial window: a tape-out alone costs tens of millions and takes roughly six months to return finished silicon (Reuters, February 2025), with design, qualification and rack integration on either side of it. The merchant vendors — NVIDIA and AMD — ship a new generation roughly annually, so a multi-year custom program is racing a moving target that is a generation or two more efficient per watt by the time the chip lands; delay does not merely slip revenue, it strands an otherwise excellent chip. Use the latest dependent wafer, memory, package and system-release dates, with a requalification owner for each alternative. Chapter 2.1 owns the integrated schedule; Chapter 1.8 owns discounted investment appraisal.

The table is a fixed-cost ladder. Merchant GPU: no buyer-funded chip-design NRE, broad programmability, and the vendor owns chip design while you retain utilization and resale risk — you pay for all of it in the unit price and the allocation queue. Full in-house silicon: maximum control and potentially lower recurring unit cost at qualified volume, paid for with the deepest fixed cost and the longest clock. The co-design middle allocates IP, yield, package test and sustaining duties through its statement of work; none disappears.

Fixed program cash is design + software + integration + commercial years × sustaining + delay reserve. Subtract custom variable cost from merchant cost on the same useful-service basis, then multiply by committed volume. Net surplus is that service saving minus fixed program cash; volume break-even is fixed cash divided by saving per device. The result below recomputes the shorter commercial window before rounding.

Fund further qualification in the base scenario; reject the lower-volume and delayed screens. A mask set cannot earn back design cash after the workload’s window closes. Obtain a statement of work, committed service volume and software ownership before sending these cash flows to investment appraisal.

The inputs are the guide’s own assumptions, declared in the stated-assumptions callout above; the work-package split (design, software, integration, sustaining) follows Synopsys’s silicon-success guidance, which supplies none of the amounts. Chapter 1.8 owns the next handoff.

Custom silicon went from a Google-only curiosity to an industry-wide wave because you no longer need Google's silicon org to do it. Broadcom and Marvell turned ASIC design into a service: they bring the hardened IP (SerDes, the highest-bandwidth interconnect and PCIe/scale-up blocks, memory controllers, packaging methodology) and the proven path through TSMC's advanced nodes and CoWoS, and the customer brings the compute architecture and the workload. This is the merchant-silicon disruption — not that hyperscalers build chips, but that buying a custom chip became a procurement line item rather than a decade-long capability build.

The market structure that resulted is a near-duopoly. Custom ASICs are projected at ~27.8% of AI-server shipments in 2026, growing ~44.6% year-over-year — nearly triple the ~16% growth of merchant GPUs (TrendForce, 2026). Behind that wave, Broadcom holds ~55–60% of the broader custom-AI-ASIC market and Marvell ~13–15%, together roughly 70–75% (J.P. Morgan estimates, via December 2024 reporting; some 2026 estimates put Broadcom nearer ~70%). Broadcom anchors Google's TPU and Meta's MTIA programs and reported AI revenue up ~143% year-over-year (Q2 FY2026) with a multi-tens-of-billions backlog; Marvell guides toward ~$11.5B in total FY2027 revenue on AI demand — its custom AI silicon is ~$1.5–2B-scale today, targeting >$10B by FY2029. The consequence for a strategist: the custom-silicon path is real and serviceable, but the on-ramp runs through two companies, and both of them — and every chip they design — sit on the same TSMC advanced-node and CoWoS/HBM allocation as the NVIDIA GPUs you were trying to escape. Building custom does not exit the supply chain; it re-enters it from a different door. → the upstream allocation gate is Chapter 7.6 (HBM) and Chapter 7.7 (packaging); procurement strategy is Chapter 2.3.

The cost advantage of a custom ASIC comes from specialization; its central risk depends on how much programmability it retains. A merchant GPU is a general matrix engine that runs whatever the compiler emits; a custom accelerator can also be compiler-programmable, while a fixed-function inference ASIC bakes in assumptions about precision, attention pattern, memory hierarchy, and collective shape, and spends the transistors it saved on flexibility to do your workload faster and cooler. That is exactly why it wins on tokens/$/W — and exactly why it is exposed when the workload moves.

One direction is fixed-function efficiency: harden the datapath to the model architecture you serve today (a specific MoE shape, a specific KV-cache layout, FP8/FP4 microscaling) and you capture the full cost-per-token advantage — for that architecture. The other is reprogrammable flexibility: keep enough generality that a new attention mechanism, a new precision format, or a shift from dense to wide-MoE does not strand the silicon — and you give back some of the efficiency that justified building at all. The cost of choosing wrong is asymmetric: a model-architecture shift that lands after tape-out cannot be patched in firmware, and a respin can add tens of millions and multiple quarters (guide scenario). The industry's own history is the cautionary tale — fixed-function accelerators that assumed a model shape have been left behind when the research frontier moved, while the parts that retained a programmable core for the matrix math survived the transition.

At the scale where a custom program pays for itself, neither an all-custom nor an all-merchant fleet is the right answer, because the two failure modes are opposite and a mix is the optimal hedge. Below a few thousand accelerators the calculus inverts and a single family usually wins on the operational tax alone (Chapter 7.1). An all-merchant fleet leaves the structural cost-per-token advantage on the table for the workloads that could capture it; an all-custom fleet is one architecture shift away from a stranded write-down. The hybrid fleet resolves the tension by routing each workload to the silicon whose stability and volume it matches.

The partition follows from the prior sections. Frozen, high-volume production inference — the stable serving tier — goes to fixed-function custom silicon, where a 30–40% price-performance advantage of the kind AWS claims for Trainium turns into roughly 23–29% lower cost at equal output. The moving frontier — pre-training, RL, research, and any model whose architecture is still in flux — stays on flexible merchant GPUs, where the generality is worth its premium because it is an option on a future you cannot yet specify. The bridge cases — new models still ramping toward stable volume, or workloads with uncertain longevity — stay on merchant GPUs until they prove durable enough to migrate to custom. The ratio between these tiers is itself the hedge: it is tuned to how much of your demand is genuinely frozen-and-huge versus how much is still moving, and it is re-decided each generation rather than committed once.

The consequence for procurement is that build-vs-buy is neither binary nor permanent. It is a continuous allocation problem: migrate a workload to custom silicon only once it crosses the volume-and-stability threshold, keep the merchant GPU as both the default and the escape hatch, and treat the custom fraction of the fleet as a position you re-balance — not a one-way door. In 2026 the operators winning on cost-per-token are not those with the most custom silicon, but those who put the right workloads on it and kept everything else flexible. → fleet composition and heterogeneous procurement is Chapter 7.11; the refresh and depreciation cadence that governs when custom silicon is retired is Chapter 14.9.