Custom ASICs & the Merchant-Silicon Disruption

The previous four chapters treated accelerators as products you select. Here silicon is something you can commission — and the only question worth asking first is whether the workload is big enough, durable enough, and stable enough to pay back a chip you must design, validate, and manufacture before it earns a cent. The merchant-GPU model (buy NVIDIA, inherit CUDA and the allocation queue) is the default because someone else paid the fixed cost. A custom ASIC inverts that bargain: you absorb the non-recurring engineering (NRE) and the lead time up front, in exchange for a chip that does exactly your workload at a lower cost per token — and nothing else. What changed in the 2025–2026 era is that for the largest inference buyers the trade flipped from speculative to obviously correct, and the merchant-silicon design houses (Broadcom, Marvell) turned chip design into a service you can buy.

The custom-silicon economics come first — NRE, lead time, minimum-volume thresholds, the breakeven against a merchant GPU — then the fixed-function-risk-vs-flexibility fork that determines whether the bet survives an architecture shift, and finally the hybrid fleet most large operators actually run. A custom ASIC is the highest-leverage and least-reversible procurement decision in Part 7. Clear the volume threshold and you own the lowest cost-per-token compute available; miss it and you own a stranded mask set and a chip that lost to the next merchant generation before it shipped. → the XPU programs themselves live in Chapter 7.4; the merchant GPUs you are deciding against are in Chapter 7.2 and Chapter 7.3.

A custom ASIC has two cost components that a merchant GPU hides from you because they are already amortized across NVIDIA's millions of units: NRE (the one-time cost to design, verify, and tape out the chip) and per-unit recurring cost (wafer, HBM, packaging, test — the same supply chain the merchant GPU draws from). The whole case for building rests on a single inequality: does the per-unit cost advantage, multiplied by your deployed volume, exceed the NRE plus the opportunity cost of the lead time? Below that threshold the program never pays back; above it, every unit past breakeven is structural margin.

NRE is the number that disciplines the decision. At the leading edge the fixed cost of a new design has exploded: a 3 nm chip costs roughly $590M to design end-to-end, against ~$416M at 5 nm and ~$217M at 7 nm (Silicon Analysts, 2026). Most of that is not the mask set — a 3 nm reticle set is ~$15M (vs ~$6.5M at 5 nm) — but the verification, validation, IP licensing, and physical-design labor that a leading-edge tape-out demands. The practitioner shorthand the industry actually quotes for a complete AI-accelerator program is ~$300M–$1B+ in NRE, depending on node, die size, chiplet count, and how much IP is bought versus built (Tom's Hardware, 2026). The cost of being wrong is steep: a single respin at a leading node runs $50–$100M and delays the product 6–12 months — which is why pre-silicon verification, not the mask, is where the money and the schedule risk concentrate.

Then the lead time. From committed architecture to silicon in a rack is 18–36 months, and that clock is where weak custom programs die. The merchant vendors ship a new generation roughly annually; a 30-month custom program is therefore racing a moving target that is two generations more efficient per watt by the time your chip lands. The lead time is not just schedule risk — it is obsolescence risk, and it is the reason custom silicon only makes sense for a workload you are confident will still exist, at scale, three years out.

The table is a fixed-cost ladder. Merchant GPU: zero NRE, maximum flexibility, and the vendor eats the obsolescence risk — you pay for all of it in the unit price and the allocation queue. Full in-house silicon: maximum control and the lowest unit cost at extreme volume, paid for with the deepest fixed cost and the longest clock. The co-design middle is what this era added.

Custom silicon went from a Google-only curiosity to an industry-wide wave because you no longer need Google's silicon org to do it. Broadcom and Marvell turned ASIC design into a service: they bring the hardened IP (SerDes, the highest-bandwidth interconnect and PCIe/scale-up blocks, memory controllers, packaging methodology) and the proven path through TSMC's advanced nodes and CoWoS, and the customer brings the compute architecture and the workload. This is the merchant-silicon disruption — not that hyperscalers build chips, but that buying a custom chip became a procurement line item rather than a decade-long capability build.

The market structure that resulted is a near-duopoly. Custom ASICs are projected at ~27.8% of AI-server shipments in 2026, growing ~44.6% year-over-year — nearly triple the ~16% growth of merchant GPUs (TrendForce, 2026). Behind that wave, Broadcom holds ~55–60% of the custom-accelerator design-services market and Marvell ~15%, together ~70–75% (J.P. Morgan, 2025–2026; some 2026 estimates put Broadcom nearer ~70%). Broadcom anchors Google's TPU and Meta's MTIA programs and reported AI revenue up ~143% year-over-year (Q2 FY2026) with a multi-tens-of-billions backlog; Marvell anchors AWS Trainium and Microsoft Maia and guides toward ~$11.5B in total FY2027 revenue on AI demand — its custom AI silicon is ~$1.5–2B-scale today, targeting >$10B by FY2029. The consequence for a strategist: the custom-silicon path is real and serviceable, but the on-ramp runs through two companies, and both of them — and every chip they design — sit on the same TSMC advanced-node and CoWoS/HBM allocation as the NVIDIA GPUs you were trying to escape. Building custom does not exit the supply chain; it re-enters it from a different door. → the upstream allocation gate is Chapter 7.6 (HBM) and Chapter 7.7 (packaging); procurement strategy is Chapter 2.3.

The cost advantage of a custom ASIC comes from the same property that creates its central risk: it is hardened. A merchant GPU is a general matrix engine that runs whatever the compiler emits; a custom inference ASIC bakes in assumptions about precision, attention pattern, memory hierarchy, and collective shape, and spends the transistors it saved on flexibility to do your workload faster and cooler. That is exactly why it wins on tokens/$/W — and exactly why it is exposed when the workload moves.

One direction is fixed-function efficiency: harden the datapath to the model architecture you serve today (a specific MoE shape, a specific KV-cache layout, FP8/FP4 microscaling) and you capture the full cost-per-token advantage — for that architecture. The other is reprogrammable flexibility: keep enough generality that a new attention mechanism, a new precision format, or a shift from dense to wide-MoE does not strand the silicon — and you give back some of the efficiency that justified building at all. The cost of choosing wrong is asymmetric: a model-architecture shift that lands after tape-out cannot be patched in firmware, and a respin is $50–100M and two to three quarters. The industry's own history is the cautionary tale — fixed-function accelerators that assumed a model shape have been left behind when the research frontier moved, while the parts that retained a programmable core for the matrix math survived the transition.

No serious operator runs an all-custom or all-merchant fleet, because the two failure modes are opposite and a mix is the optimal hedge. An all-merchant fleet leaves the structural cost-per-token advantage on the table for the workloads that could capture it; an all-custom fleet is one architecture shift away from a stranded write-down. The hybrid fleet resolves the tension by routing each workload to the silicon whose stability and volume it matches.

The partition follows from the prior sections. Frozen, high-volume production inference — the stable serving tier — goes to fixed-function custom silicon, where it captures the 30–50%+ cost-per-token advantage. The moving frontier — pre-training, RL, research, and any model whose architecture is still in flux — stays on flexible merchant GPUs, where the generality is worth its premium because it is an option on a future you cannot yet specify. The bridge cases — new models still ramping toward stable volume, or workloads with uncertain longevity — stay on merchant GPUs until they prove durable enough to migrate to custom. The ratio between these tiers is itself the hedge: it is tuned to how much of your demand is genuinely frozen-and-huge versus how much is still moving, and it is re-decided each generation rather than committed once.

The consequence for procurement is that build-vs-buy is neither binary nor permanent. It is a continuous allocation problem: migrate a workload to custom silicon only once it crosses the volume-and-stability threshold, keep the merchant GPU as both the default and the escape hatch, and treat the custom fraction of the fleet as a position you re-balance — not a one-way door. In 2026 the operators winning on cost-per-token are not those with the most custom silicon, but those who put the right workloads on it and kept everything else flexible. → fleet composition and heterogeneous procurement is Chapter 7.11; the refresh and depreciation cadence that governs when custom silicon is retired is Chapter 14.9.