On-Package Power Delivery & Power Integrity

Everything upstream — the substation, the 800 VDC spine, the busbar, the power shelf — exists to deliver clean voltage to the pins of the accelerator package. The accelerator does not run on the 48V it receives there; its core rail sits around 0.6–0.9V, and at the power levels of a 2026-class GPU that means a steady-state core current in the thousands of amps (peak demands reach ~2,000A today, with typical parts in the 500–2,000A band; roadmap parts push past 2,000A). On-package power delivery converts 48V to sub-1V at multi-kiloamp current, as physically close to the die as manufacturing allows, while holding the rail flat through load steps that swing hundreds of amps in nanoseconds — the least-visible, highest-stakes meter of the entire power chain.

The action here plays out at the millimeter and microsecond scale. The path runs from board 48V down to core (multiphase VRMs and smart power stages), through the architectural fork between lateral and vertical power delivery and the silicon-level move to backside power (BSPDN), to the PDN impedance target and the decoupling hierarchy that meets it, and finally to the physics of the load-line, Vdroop, and the di/dt event. That last one reads end-to-end: the on-die di/dt event is the same physical phenomenon that, summed across 72 GPUs stepping in lockstep, becomes the synchronized facility transient the BBU/BESS spine must absorb. Guess wrong at any layer and you either strand silicon performance or present a grid-disturbing load that earns a worse interconnection deal.

The conventional answer, inherited from the server world, is the multiphase buck VRM: a digital controller drives N interleaved phases, each phase a high-side/low-side MOSFET pair (now integrated as a smart power stage, or DrMOS, with current/temperature telemetry built in) feeding an inductor, all summing into a shared output rail. Interleaving the phases multiplies the effective switching frequency at the output and shrinks the output ripple, so more phases buy you a tighter rail and more current — at the cost of board area, gate-drive losses, and controller complexity. A modern GPU core rail can demand 16, 20, or more phases just to source the current without melting any single power stage.

Two design moves dominate here. First, 48V direct conversion versus a two-stage 48V→12V→core path: the industry has decisively moved to higher distribution voltage (48V over the legacy 12V) because at constant power, quadrupling the voltage cuts distribution current by 4x and therefore I²R loss in the board copper by 16x. Direct 48V-to-core conversion (single-stage) saves the intermediate-bus-converter losses but stresses the duty cycle; two-stage is more forgiving but adds a conversion. Second, the load-line (also called adaptive voltage positioning): deliberately programming the regulator so the delivered voltage droops with load current along a defined slope. This is counterintuitive — you are intentionally lowering voltage as current rises — but it can reduce the transient excursion by pre-positioning the rail within the negotiated load-line budget, and it lets the silicon run at the lowest voltage that still meets timing, which is pure power savings. The load-line slope is a negotiated number between the silicon vendor (who owns the timing margin) and the power team (who owns the regulator), and getting it wrong either burns power or causes timing failures under transient.

Where the final 48V-to-core conversion physically sits is the central architectural choice, three placements whose current path, thermal path and service boundary must be compared.

Board-edge multiphase is the legacy position: the VRM lives on the motherboard, current travels through the socket/connector and across the package to the die. Cheap, serviceable, well-understood — and increasingly untenable as core current climbs, because the PDN resistance from board edge to die dominates the loss budget. Lateral power-on-package moves current-multiplier modules onto the package substrate itself, flanking the die on the north/south or east/west edges, so the final conversion happens millimeters away. Vertical power delivery (VPD) is one placement option: the conversion modules sit directly underneath the processor, feeding current straight up into the die with the shortest possible path. ASE patent US11848296B2 (published December 19, 2023) models one embodiment with 66% lower ESR and 42.8% lower ESL. That result cannot establish total-system efficiency: the rail and shelf loss ledger must keep their boundaries separate.

A separate silicon-level choice is backside power delivery network (BSPDN) — routing the power rails on the back of the wafer, beneath the transistors, instead of competing for the same congested metal stack as signal routing on top. Intel ships it as PowerVia on the 18A node (in Panther Lake client parts as of early 2026); TSMC's Super Power Rail arrives with the A16 node, whose volume production slipped to 2027 on TSMC's April-2026 roadmap (from an original 2H-2026 target); Samsung's SF2Z targets 2027. The payoff is twofold: Intel’s particular test chip reported roughly 30% lower IR droop. This is not a converter-efficiency gain. Moving power routing to the backside also frees frontside tracks for signals. Together, lower droop and more signal-routing space improve power integrity and logic density. The catch is thermal — the selected backside stack and cooling orientation determine which layers lie between active devices and the cold plate, complicating the already-tight thermal budget covered in Chapter 5.4.

The table is a current-path comparison. As core current climbs generation over generation, the loss in any position grows as I², making resistance and transient control more consequential. VPD and BSPDN address different boundaries; a roadmap 600 kW Kyber rack rating cannot by itself choose a GPU converter position. At 2,000 A and an assumed 100 µΩ path, I²R = (2,000 A)² × 100 × 10⁻⁶ Ω = 400 W in that path, not a percentage of rack loss. The density ramp covered in Chapter 7.1 is, at the package level, a rail-current and thermal-budget test of these choices.

Power integrity reduces to one specification: hold the core rail inside its noise window across every frequency at which the load draws current. The load is a digital engine that switches at GHz and gates entire tiles on and off at MHz, so its current demand has spectral content from DC up past 100 MHz. The governing design rule is the target impedance: Z_target = ΔV_allowed / ΔI_max. For a sub-1V rail with a tight noise budget and a multi-hundred-amp transient, that target lands in the sub-milliohm range — often well under 1 mΩ out to 100 MHz, and into the microohm range at DC. The job of the PDN is to present a flat impedance below that line across the whole band. Any frequency where impedance pokes above the line is a frequency where a load step produces a droop that violates the noise budget — and droop, in a clocked machine, means a timing failure, which means you either lower the clock (lost performance) or raise the voltage (lost power).

No single component holds sub-milliohm flat across nine decades of frequency, so the PDN is a hierarchy of decoupling, each tier owning a frequency band:

• Bulk capacitance (board, µs–ms band): large electrolytic/polymer caps near the VRM that hold the rail through the regulator's own control-loop response time. This is also where the load-step ride-through energy lives.
• Mid-frequency ceramics (package + board, ~MHz band): MLCCs spread across the package and board backside, bridging the gap between bulk caps and on-die caps. This band is where anti-resonance bites: the parasitic inductance of one tier resonates against the capacitance of the next, producing an impedance peak exactly where you need a valley.
• On-die decoupling (>100 MHz band): MIM and deep-trench capacitors integrated into the silicon, the only thing fast enough to respond to the highest-frequency current steps. As package and board parasitic inductance increasingly dominate, the burden shifts on-die — and the newest accelerators add on-die voltage telemetry to report rail quality in real time so the system can adapt.

The decision here is the on-package capacitance budget: how much die area and package real estate you spend on decoupling versus logic and signal. Spend too little and you fail target impedance and droop; spend too much and you sacrifice die area (the most expensive real estate on the package) or package complexity. This budget is co-designed with the load-line slope and the VRM phase count — three knobs that together must close the impedance target.

The physics ties it all together. A GPU running a synchronous training step does not draw constant current; it draws current that tracks the workload: when thousands of cores fire together at the start of a matrix-multiply tile, current can step hundreds of amps in nanoseconds to microseconds. That rate of change of current is di/dt, and across the inductance of the PDN it generates a voltage transient: V = L·di/dt. A fast load step pulls the rail down (Vdroop); the sudden release at the end of a compute burst lets it overshoot up. Either excursion outside the noise window is a fault.

Three lines of defense, in order of speed. On-die capacitance handles the fastest edge — it is the only charge reservoir close enough to respond in nanoseconds. The load-line pre-positions the rail so the droop lands inside budget rather than below it. Adaptive clocking / droop detection is the last resort: dedicated on-die circuits sense an impending droop and momentarily stretch the clock to ride it out, trading performance for rail margin within the validated protection behavior; excessive droop can still fault. The accelerator vendor co-designs all three; the data-center engineer inherits the result as a power profile — a characteristic spike-and-idle waveform whose contracted amplitude, duration, repetition and slew must be supplied and tested, because they have consequences three layers up.

Core output = 0.80 V × 2,000 A = 1.6 kW; path loss = (2,000 A)² × 20 µΩ = 80 W. The 1,000 A step adds 20 mV resistive drop and 10 pH × (1,000 A/1 µs) = 10 mV inductive drop: 30 mV against the 40 mV allowance. Shelf input = 120/0.96 = 125 kW, with 5 kW conversion heat. The added 20 kW for 10 ms needs 200 J. The ideal requirement C ≥ 2×200/(50²−46²) F lies between 1.0 and 1.1 F: 1.0 F supplies 192 J and fails, while 1.1 F supplies about 210 J and clears this ideal screen. At 95% efficiency shelf input is about 126 kW and fails; 96% is the exact input-power threshold. Capacitance does not reduce steady input energy.

Keep the path and shelf candidates for dynamic validation; measure impedance, control-loop response, capacitor tolerance/ESR, protection and repeated-pulse duty. Do not add the 80 W rail loss to an independently quoted shelf boundary without tracing where that loss is already included. Hand the complete loss ledger to 4.1 and the rack waveform/interface to 4.7.

Method: Texas Instruments, power-management fundamentals. Chapter 4.7 owns the next handoff.

On-package power delivery is the terminal node of a chain that this guide reads end-to-end. Upstream of the package, the 800 VDC spine, the disaggregated sidecar power, and the busbar that feed the shelf are covered in Chapter 4.7; the LV distribution, PDUs, and rack power that deliver 48V to the board are in Chapter 4.6; and the UPS / energy-storage layer that absorbs the slow envelope of the transient — the facility end of the di/dt spine that starts on the die in this chapter — is in Chapter 4.5. The accelerator whose rail we are feeding is taxonomized in Chapter 7.1; the thermal path that now runs through the backside power layer is engineered in Chapter 5.4 against the density wall of Chapter 5.1. The forward roadmap — where core current, VPD adoption, and BSPDN go through 2030 — is consolidated in Chapter 16.2.