Patent US11848296B2 describes a vertical package power-delivery embodiment with ESR/ESL reductions of 66%/42.8%
66% / 42.8% in patent embodimentmodeled
| Value kind | modeled — Interpret this value according to its displayed kind, scope, source, and as-of date. |
|---|---|
| Scope | Specific patent embodiment and comparison; no general rack efficiency, power-loss or availability guarantee. |
| As of | 2023-12-19 |
| Source | Advanced Semiconductor Engineering (ASE) — Patent disclosure and simulated impedance example; not a Vicor production system measurement. · Description after Figure 5: simulated impedance curve and ESR/ESL reduction paragraph |
| Review | checking…review by 2027-09-05 · standard cadence |
| Recorded changes | last 2026-09-16 · 2 revisions tracked |
| Claim id | pdn-esr-esl-reduction-from-vertical-vs-lateral |
Where the guide uses it
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