Power Topology Foundations & Voltage Selection

Power reaches a GPU only after a relay of voltage transformations, and every link in that relay is a decision with a price. High-voltage transmission arrives at the fence; an on-site substation steps it down to medium voltage; transformers drop it to low voltage; a UPS conditions it; a PDU or busway distributes it; a power shelf rectifies it to a DC bus; an on-board VRM bucks that bus down to the sub-volt rail the silicon actually runs on. Seven or eight conversions, each shedding a percent or two of efficiency, each demanding copper, floor area, cooling, and a slice of the capital stack. The chapter that follows is about where you set the voltages and how many times you convert — because in a power-bound era, the conversion you avoid is worth more than the one you optimize.

This chapter walks the end-to-end chain link by link; builds the voltage taxonomy that names every rail (HV/MV/LV on the AC side, 12 V / 48-54 V / ±400 V / 800 V on the DC side) and accounts for the stages between them; then confronts the two forks that dominate the design basis. The first is the region you build in. 50 Hz IEC versus 60 Hz ANSI re-ratios your transformers, re-sizes your conductors, re-codes your protection, and re-prices your switchgear lead times. The second is the AC-to-the-rack versus DC-disaggregated architecture, the choice that decides how many conversion stages survive into 2027. The chapter closes on designing to the real peak (EDPp, not TDP), the per-rack density tiers that set the substrate, and the lead-time reality that reshapes topology before any of the engineering matters.

Before any fork, fix the map. A hyperscale AI campus moves power through a fixed sequence of stages, and you cannot understand a topology decision without knowing which stage it touches. The canonical chain, utility to chip:

• HV transmission → on-site substation. Power arrives at 115–500 kV (or 132–400 kV in IEC regions) and a customer- or utility-owned substation steps it to medium voltage. This is the scarcest, longest-lead, least-reversible link — the interconnection queue and the substation are the schedule. → Chapter 4.2.
• MV distribution. 11/13.8/33/34.5 kV class busses the power across the campus to pad-mounted or block transformers. Radial, primary-selective, or ring — the architecture here sets the campus single-line and the fault-current picture. → Chapter 4.2.
• LV / transformer. The block/unit transformer drops MV to the distribution LV class — 400 V (IEC) or 480 V (ANSI) three-phase — the voltage that actually feeds the white space. AI's 100%-non-linear load makes this transformer a harmonics problem, not just a ratio. → Chapter 4.4.
• UPS. Double-conversion or eco-mode conditioning and ride-through sits between the transformer and the load (in AC architectures) or is being displaced toward rack BBUs and facility BESS in DC ones. → Chapter 4.5.
• PDU / busway → rack. Overhead busway or cable-and-PDU carries LV to the rack, where a rack PDU (commonly 415 V three-phase, A/B dual-fed) lands it on the racks. → Chapter 4.6.
• DC bus → VRM → chip. A power shelf rectifies AC to the in-rack DC bus (48/54 V today, ±400/800 V in the DC-disaggregated future); the VRM/VRD on the board bucks that bus to the <1 V GPU core rail at hundreds of amps. The last conversion is the most thermally and electrically brutal. → Chapter 7.12.

The whole guide's Part 4 is organized around these links. This chapter's job is the meta-decision that sits above all of them: how many of these stages exist at all, and at what voltage.

Voltage is taxonomized by class on the AC side and by rail on the DC side, and the two taxonomies meet at the rectifier. On the AC side, the IEC convention runs HV (above 35 kV, transmission and primary distribution), MV (1–35 kV, campus distribution), and LV (below 1 kV — the 400/480 V that feeds the hall). The DC side is where the 2026 action is: the legacy in-rack bus is 12 V (enterprise servers) or 48–54 V (OCP / GPU racks, the de-facto standard since the Open Rack V3 era), and the disaggregated future is ±400 VDC (the EV-supply-chain-leveraged sidecar standard, OCP Mt Diablo) and 800 VDC (the NVIDIA Kyber-class reference for megawatt racks).

The reason voltage matters so much is the conductor. Power is voltage times current, and resistive loss is current squared times resistance — so for a fixed power, raising the voltage cuts the current linearly and the I²R loss quadratically. NVIDIA's own 800 VDC accounting puts numbers on it: moving from 54 V in-rack distribution toward an 800 VDC path lets you push ~85% more power through the same conductor or carry the same power with ~45% less copper, while collapsing the conversion chain from roughly four stages to two and lifting end-to-end efficiency by up to ~5 points (NVIDIA, 800 VDC Architecture, 2025–2026). At a gigawatt, 5 points is 50 MW you never had to generate, cool, or pay for.

Conversion-stage accounting is the discipline that makes this concrete. You count, end to end, every place the voltage changes and every place AC becomes DC or vice versa, and you assign each stage an efficiency and a cost. The legacy AC chain — MV transformer → LV → UPS double-conversion (AC→DC→AC) → PDU → rack PSU (AC→DC) → VRM (DC→DC) — carries five to seven loss-bearing stages and lands a legacy facility anywhere from ~61% to ~87.5% efficient utility-to-VRM (SemiAnalysis, Datacenter Anatomy Pt 1). A modern 800 VDC chain that rectifies once at the facility perimeter (ideally in a solid-state transformer) and distributes DC the rest of the way clears 92%. What moves the headline is the number of stages you deleted, not any single stage's efficiency.

This guide is global, and the single most under-appreciated fact about power topology is that the region reshapes it before any engineering judgment enters. The world runs two electrical systems, and a data center inherits one of them wholesale. The IEC world (Europe, most of Asia, Africa, Australia, much of South America) is 50 Hz, with LV distribution at 400 V three-phase / 230 V single-phase, system earthing per the TN-S / TT / IT taxonomy, and protection and equipment built to IEC 60364, IEC 61439, and the IEC 61850 substation-automation stack. The ANSI/NEC world (North America, parts of Latin America, Saudi Arabia, the Philippines, and a scattering of others) is 60 Hz, with LV distribution at 480 V three-phase / 277 V single-phase, grounding and protection per the NEC (NFPA 70), and switchgear to ANSI/IEEE standards.

The consequences cascade. The frequency sets transformer flux and therefore core size — a 50 Hz transformer is physically larger and heavier than a 60 Hz one of equal rating, which changes pad loading and crane plans. The LV voltage (400 vs 480 V) re-ratios every step-down transformer and, because power is fixed, re-sizes every feeder: 480 V carries the same kW at ~17% less current than 400 V, so an identical hall wired to ANSI uses meaningfully less copper in its LV runs. The earthing regime — whether you bond the neutral solidly (TN-S), through impedance, or leave it isolated (IT) — governs touch voltage, fault detection, and how the whole protection scheme behaves; this is engineered in depth in Chapter 4.11, but it is chosen here, by region. And the code regime dictates which switchgear, which breakers, and which arc-flash methodology you can even procure — an IEC-spec GIS lineup and an ANSI-spec metal-clad lineup are different supply chains with different lead times.

The fork is not a choice you make; it is a constraint you receive. But it is a constraint you must price at scoping time, because a design developed against the wrong basis — a US template dropped onto a Frankfurt site, or vice versa — fails diligence and re-engineers late, when re-engineering is most expensive.

Inside whichever regional basis you inherit sits the live 2026 decision: how the last several stages of the chain are arranged. There are two coherent answers, and they diverge on the number of conversions, the location of the rectifier, and the maturity of the ecosystem.

The legacy AC-to-the-rack path keeps AC all the way to the cabinet. MV transforms to 400/480 V LV; a facility UPS conditions it; busway or PDU carries AC to the rack; and an in-rack power shelf rectifies AC to the 48/54 V DC busbar that feeds the boards. This is the proven, fully-stocked path — every vendor ships it, every electrician can build it, every code official has approved it — but it carries the most conversion stages and rectifies once per rack, multiplying PSU count, fan count, and maintenance surface across thousands of cabinets.

The DC-disaggregated path moves the rectification upstream and out of the rack. In the OCP Mt Diablo / ±400 VDC pattern (championed by Google and Microsoft), a centralized sidecar power unit converts to ±400 VDC and feeds disaggregated DC to the IT racks, leveraging the EV industry's 400 V supply chain. In the NVIDIA 800 VDC / Kyber pattern, a solid-state transformer (or staged rectifier) converts MV grid power directly to 800 VDC at the facility level, and the rack carries a single high-ratio DC-DC stage to the board rail. Both delete the per-rack AC rectifier, both cut conversion stages from ~four to ~two, and both are the only viable way to feed the >500 kW — >1 MW racks on the roadmap. The cost is ecosystem immaturity: DC breakers, DC-rated busways, >1 kV-DC UL listings, and SST production are all still ramping in 2026, so the disaggregated path trades a thinner vendor bench and code-pioneering risk for its efficiency and density headroom. The full engineering of this transition — including the solid-state transformer and sidecar power — lives in Chapter 4.7 (with SST harmonics context in Chapter 4.4).

The most common way an AI power chain is mis-sized is to design it to the chip vendor's TDP — the thermal design power, a steady-state-ish number meant to size a heat sink — rather than to EDPp, the electrical design power at peak, which is what a synchronized GPU fleet actually pulls from the bus. The two diverge violently in AI halls. A training cluster running synchronous collectives steps in lockstep: thousands of GPUs ramp from a near-idle inter-step lull to full compute on the same clock edge, then back, many times a second. The aggregate load is a square wave whose peaks overshoot nameplate, with transients that slam the bus on every all-reduce boundary, not a smooth TDP plateau.

Designing the conductors, breakers, UPS, and transformer to TDP leaves no margin for the overshoot, and the chain nuisance-trips on protection or sags on the transient exactly when the cluster is most expensive to interrupt. Designing to EDPp means sizing for the synchronized peak and engineering the transient explicitly — which is why modern racks carry on-package and BBU-level capacitance (e.g. NVIDIA's GB300 NVL72 cites ~65 J/GPU of energy storage to shave ~30% off the grid-side peak) and why facility BESS is increasingly a power-quality device, not just a runtime device. The headroom numbers tell the story: practitioners report needing roughly 3% power oversubscription headroom for steady training versus ~21% for bursty inference profiles (Uptime Institute). The transient itself — its origin on the die, its propagation, and the chip→BBU→BESS mitigation spine — is the canonical subject of Chapter 4.5, with the on-die origin in Chapter 7.12. The point for this chapter is upstream of all of it: the number you put on the single-line, the breaker, and the transformer is EDPp, and getting that number wrong propagates a fault through every stage you just designed.

Voltage architecture is downstream of one number you must commit early: the per-rack density tier the facility is built to absorb. The 2026 roadmap is steep and well-published, and it is the reason the AC/DC fork is urgent rather than academic. A hall whose substrate — substation capacity, MV ring ampacity, conductor pathways, floor loading — is scoped to one generation strands the next.

• ~40 kW/rack — H100-era air-cooled racks (2023). Legacy AC-to-the-rack at 415 V is entirely adequate; this is the world most existing halls were built for.
• ~120–142 kW/rack — GB200/GB300 NVL72 (2024–2025). 48/54 V DC busbar, liquid cooling mandatory, and the LV/PDU chain near its practical ceiling. Still feasible on AC-to-the-rack with high-amperage busway.
• ~190–230 kW/rack — Rubin VR200-class (2026). The point where ±400 VDC disaggregation starts to pay for itself on conductor and PSU count.
• ~600 kW → 1 MW+/rack — Rubin Ultra Kyber-class (2027) and beyond. 800 VDC is not optional here; the AC-to-the-rack path cannot deliver this current at the cabinet without absurd copper. This tier is the reason the irreversible substrate must be designed for DC even when the IT layer is not yet.

The design discipline mirrors the reversible/irreversible split from Part 1: pour the substation, MV ring, pathway, and floor-loading basis for the high-density DC endpoint you cannot retrofit, while fitting out the rack-level voltage architecture (which you can swap at refresh) to the generation you are actually buying. Build the chain for 40 kW and you have built an inference-only, current-generation building; reserve the headroom for the ramp and you keep the ramp open.

One more force reshapes topology before any of the above engineering is decided: what you can actually buy, and when. Power-chain equipment carries some of the longest lead times in the entire build, and in a power-bound market the lead time is the design constraint. HV and substation power transformers run ~128–144 weeks standard, stretching to ~60 months in constrained markets (Wood Mackenzie) — the schedule-dominating long pole that often decides the energization date. MV switchgear, large UPS modules, and SST/DC gear all carry multi-quarter-to-multi-year queues, and the newer DC-disaggregated equipment is precisely the thinnest-supplied.

The consequence is that procurement reshapes topology in two directions. First, it pulls toward fewer, more available stages — a topology that needs three exotic transformers you cannot get for four years is just a delay. Second, it can pull toward the DC path or away from it depending on the calendar: the AC-to-the-rack ecosystem is fully stocked today, while the SST/800 VDC ecosystem is ramping — so a 2026 ground-break may be forced onto AC distribution for the IT layer even as it builds the substrate for DC. Every long-lead power item belongs in the lead-time register maintained in Chapter 2.3, and the voltage architecture you commit to should be cross-checked against that register before it is frozen. The most elegant single-line on the drawing is worthless if its critical equipment energizes after the depreciation clock has already started.