Power Topology Foundations & Voltage Selection

Power reaches a GPU only after a relay of voltage transformations, and every link in that relay is a decision with a price. High-voltage transmission arrives at the fence; an on-site substation steps it down to medium voltage; transformers drop it to low voltage; a UPS conditions it; a PDU or busway distributes it; a power shelf rectifies it to a DC bus; an on-board VRM bucks that bus down to the sub-volt rail the silicon actually runs on. Each voltage-conversion stage has architecture-specific efficiency; PDU and busway distribution do not convert voltage, but still demand copper, floor area, cooling, and a slice of the capital stack. Where you set the voltages and how many times you convert is the design question — and in a power-bound era, avoiding a conversion stage beats optimizing one.

Two forks dominate the design basis. The first is the region you build in: grid frequency and the locally adopted IEC-, ANSI-/IEEE-, or other standards affect equipment ratings and protection, but frequency and standards family are separate attributes; the regional basis also re-prices your switchgear lead times. The second is the AC-to-the-rack versus DC-disaggregated architecture, which decides how many conversion stages survive into 2027. Around those two the chapter builds the voltage taxonomy that names every rail (HV/MV/LV on the AC side, 12 V / 48-54 V / ±400 V / 800 V on the DC side), then turns to designing for the real peak (EDPp, not TDP), the per-rack density tiers that set the substrate, and the lead-time reality that reshapes topology before any of the engineering matters.

Before any fork, fix the map. A hyperscale AI campus moves power through a sequence of functions whose packaging changes with the topology, and you cannot understand a topology decision without knowing which stage it touches. The canonical chain, utility to chip:

• HV transmission → on-site substation. Power arrives at 115–500 kV (or 132–400 kV in IEC regions) and a customer- or utility-owned substation steps it to medium voltage. This is the scarcest, longest-lead, least-reversible link — the interconnection queue and the substation are the schedule. → Chapter 4.2.
• MV distribution. 11/13.8/33/34.5 kV class busses the power across the campus to pad-mounted or block transformers. Radial, primary-selective, or ring — the architecture here sets the campus single-line and the fault-current picture. → Chapter 4.2.
• LV / transformer. The block/unit transformer drops MV to the distribution LV class — 400 V (IEC) or 480 V (ANSI) three-phase — the voltage that actually feeds the white space. AI's switch-mode load makes the offered harmonic spectrum and synchronized load envelope transformer inputs, not just the voltage ratio; active-PFC equipment can draw low-distortion current. → Chapter 4.4.
• UPS. Double-conversion or eco-mode conditioning and ride-through sits between the transformer and the load (in AC architectures) or is being displaced toward rack BBUs and facility BESS in DC ones. → Chapter 4.5.
• PDU / busway → rack. Overhead busway or cable-and-PDU carries LV to the rack, where a rack PDU (commonly 415 V three-phase, A/B dual-fed) lands it on the racks. → Chapter 4.6.
• DC bus → VRM → chip. A power shelf rectifies AC to the in-rack DC bus (48/54 V today, ±400/800 V in the DC-disaggregated future); rack and board DC/DC conversion first produces intermediate rails; the final VRM/VRD bucks its own input to the <1 V GPU core rail at hundreds of amps. The last conversion is the most thermally and electrically demanding. → Chapter 7.12.

The whole guide's Part 4 is organized around these links. This chapter's job is the meta-decision that sits above all of them: how many of these stages exist at all, and at what voltage.

Voltage is taxonomized by class on the AC side and by rail on the DC side, and the two taxonomies meet at the rectifier. On the AC side, voltage-class boundaries depend on the governing IEC document and application; for example, IEC low voltage extends through 1 kV AC, while project and utility usage of MV/HV must be stated rather than inferred from one universal 35 kV boundary. The 400/480 V feed to the hall is low voltage. The DC side is where the 2026 action is: the legacy in-rack bus is 12 V (enterprise servers) or 48–54 V (OCP / GPU racks, the de-facto standard since the Open Rack V3 era), and the disaggregated future is an 800 V rail-to-rail class implemented as bipolar ±400 V about a midpoint (OCP Mt Diablo) or as a unipolar nominal 800 V bus in other reference architectures.

Voltage matters because of the conductor. Power is voltage times current, and resistive loss is current squared times resistance — so for a fixed power, raising the voltage cuts the current linearly and the I²R loss quadratically. NVIDIA's own 800 VDC accounting puts numbers on it: moving from 415 VAC distribution to an 800 VDC path reported 157% more power through the same wire gauge or roughly 61% less copper for the vendor's stated topology, conductor-count and loss basis; recompute for the project one-line and route, while its reported up-to-~5-point efficiency gain uses a vendor-specific boundary; the complete illustrative ledger below counts four AC functional packages versus three integrated MV/DC packages, including final conversion (NVIDIA, 800 VDC Architecture, 2025–2026). Treat that 157% as basis-specific rather than a constant: Chapter 4.7 works the same comparison on the same October-2025 basis — its May-2025 predecessor gave ~+85% on a different conductor basis — and shows how to compute the figure for your own conductor count and route. At a fixed gigawatt of input, 5 efficiency points is 50 MW more useful output; at fixed chip output, divide by each chain efficiency before claiming avoided generation, cooling or cost.

Conversion-stage accounting makes this concrete. You count, end to end, every place the voltage changes and every place AC becomes DC or vice versa, and you assign each stage an efficiency and a cost. The legacy AC chain — MV transformer → LV → UPS double-conversion (AC→DC→AC) → rack PSU (AC→DC) → VRM (DC→DC) — carries four functional conversion packages, including the UPS’s internal AC→DC→AC stages and yields about 80–87% utility-to-VRM for the four stated stages; a representative 0.99×0.94×0.96×0.92 path is about 82%. Any LV distribution or busway loss must be a separate explicit multiplier. The separate SemiAnalysis May 26, 2026 SST/800 VDC model reports ~87%; the guide’s three-package case below also rounds to 87% from explicitly assumed stage efficiencies. Neither proves a five-point plant improvement without matching boundaries and load. What moves the headline is the product of the retained efficiencies: deleting a package can help, but a lossy high-ratio converter or extra route loss can erase the gain.

This guide is global, and the local design basis reshapes power topology before any engineering judgment enters. Specify six fields independently: grid frequency, nominal voltages, adopted installation code, equipment and product standards, earthing, and utility grid code. For example, one project basis may pair 50 Hz with 400 V three-phase / 230 V single-phase, IEC 60364 installation rules, IEC 61439 assemblies, a selected TN-S, TT, or IT earthing arrangement, and IEC 61850 utility automation where applicable; another may pair 60 Hz with 480 V three-phase / 277 V single-phase, NEC (NFPA 70), and ANSI/IEEE equipment standards. Build the equipment schedule from the adopted project basis; neither IEC lineage nor equipment frequency follows from a two-region label.

The consequences cascade. The frequency sets transformer flux and therefore core size — for otherwise unchanged transformer flux density and volts per turn, 50 Hz requires more core area than 60 Hz; offered mass and dimensions still govern pad loading, transport and crane selection. The LV voltage (400 vs 480 V) re-ratios every step-down transformer and, because power is fixed, re-sizes every feeder: 480 V carries the same kW at ~17% less current than 400 V, so an identical hall distributed at 480 V carries less current through its LV runs. The earthing regime — whether you bond the neutral solidly (TN-S), through impedance, or leave it isolated (IT) — governs touch voltage, fault detection, and how the whole protection scheme behaves; this is engineered in depth in Chapter 4.11, but it is selected in the project design basis, not inferred from region. And the code regime dictates which switchgear, which breakers, and which arc-flash methodology you can even procure — an IEC-spec GIS lineup and an ANSI-spec metal-clad lineup are different supply chains with different lead times.

You inherit the grid and adopted code, then select compatible voltages, standards, earthing, and equipment. But you must price it at scoping time, because a design developed against the wrong basis — a US template dropped onto a Frankfurt site, or vice versa — fails diligence and re-engineers late, when re-engineering is most expensive.

Inside whichever regional basis you inherit sits the live 2026 decision: how the last several stages of the chain are arranged. There are two coherent answers, and they diverge on the number of conversions, the location of the rectifier, and the maturity of the ecosystem.

The legacy AC-to-the-rack path keeps AC all the way to the cabinet. MV transforms to 400/480 V LV; a facility UPS conditions it; busway or PDU carries AC to the rack; and an in-rack power shelf rectifies AC to the 48/54 V DC busbar that feeds the boards. This is the proven, fully-stocked path — every vendor ships it, every electrician can build it, every code official has approved it — but it carries the most conversion stages and rectifies once per rack, multiplying PSU count, fan count, and maintenance surface across thousands of cabinets.

The DC-disaggregated path moves the rectification upstream and out of the rack. In the OCP Mt Diablo / ±400 VDC pattern (championed by Google and Microsoft), a centralized sidecar power unit converts to ±400 VDC and feeds disaggregated DC to the IT racks, leveraging the EV industry's 400 V supply chain. In the NVIDIA 800 VDC / Kyber pattern, a solid-state transformer (or staged rectifier) converts MV grid power directly to 800 VDC at the facility level, and the rack carries a single high-ratio DC-DC stage to the board rail. Both move the per-rack AC rectifier upstream; an AC-fed sidecar need not delete the upstream transformer or UPS. The direct-MV/DC example counts four AC functional packages versus three DC packages through final conversion. NVIDIA’s May 20, 2025 roadmap targeted 1 MW IT racks and beyond starting in 2027; qualify the named supplier’s interface rather than treating that forecast as a universal topology rule. The cost is ecosystem immaturity: DC breakers, DC-rated busways, >1 kV-DC UL listings, and SST production are all still ramping in 2026, so the disaggregated path trades a thinner vendor bench and code-pioneering risk for its efficiency and density headroom. The full engineering of this transition — including the solid-state transformer and sidecar power — lives in Chapter 4.7 (with SST harmonics context in Chapter 4.4).

The most common way an AI power chain is mis-sized is to design it to the chip vendor's TDP — the thermal design power, a steady-state-ish number meant to size a heat sink — rather than to EDPp, the electrical design power at peak, which is what a synchronized GPU fleet actually pulls from the bus. The two diverge violently in AI halls. A training cluster running synchronous collectives steps in lockstep: thousands of GPUs ramp from a near-idle inter-step lull to full compute on the same clock edge, then back, many times a second. The aggregate load is a square wave whose peaks overshoot nameplate, with transients that slam the bus on every all-reduce boundary, not a smooth TDP plateau.

Designing the conductors, breakers, UPS, and transformer to TDP leaves no margin for the overshoot, and the chain nuisance-trips on protection or sags on the transient exactly when the cluster is most expensive to interrupt. Designing to EDPp means sizing for the synchronized peak and engineering the transient explicitly — which is why modern racks place transient storage at distinct layers (NVIDIA's GB300 NVL72 integrates ~65 J/GPU of electrolytic storage in its power-shelf PSUs, reducing the measured Megatron LLM grid-side peak by 30%, while rack BBUs remain separate) and why facility BESS is increasingly a power-quality device, not just a runtime device. The headroom numbers tell the story the other way round: Azure's fleet analysis found only ~3% unused power headroom available for oversubscription across its training fleet against ~21% across its inference fleet (Patel et al., Microsoft Azure, ASPLOS 2024). That is a measure of the slack each fleet left on the table, not a margin either workload requires — size against your own measured envelope and the capping policy that enforces it. The transient itself — its origin on the die, its propagation, and the chip→BBU→BESS mitigation spine — is the canonical subject of Chapter 4.5, with the on-die origin in Chapter 7.12. For this chapter the point sits upstream of all of it: the numbers on the single-line, breaker and transformer come from the continuous, peak-versus-duration and recovery envelopes at their own boundaries; EDPp is one input, translated through the actual conversion and storage controls, and getting it wrong propagates a fault through every stage you just designed.

Voltage architecture is downstream of one number you must commit early: the per-rack density tier the facility is built to absorb. The 2026 roadmap is steep and well-published, and it is the reason the AC/DC fork is urgent rather than academic. A hall whose substrate — substation capacity, MV ring ampacity, conductor pathways, floor loading — is scoped to one generation strands the next.

• ~40 kW/rack — H100-era air-cooled racks (2023). Legacy AC-to-the-rack at 415 V is entirely adequate; this is the world most existing halls were built for.
• 132 kW nominal — HPE GB200 NVL72.
• 135 kW TDP / 155 kW peak / up to 142 kW facility basis — GB300 NVL72. 48/54 V DC busbar, liquid cooling mandatory, and the LV/PDU chain near its practical ceiling. Still feasible on AC-to-the-rack with high-amperage busway.
• 188 kW Max Q / 228 kW Max P / 330 kW facility basis — VR200 NVL72 (2026). Size irreversible infrastructure to the facility basis; run energy models on the operating profile.
• ~600 kW facility planning point — Rubin Ultra / Kyber (H2 2027 roadmap) and later. NVIDIA's Kyber roadmap pairs this tier with 800 VDC because extending 54 V distribution would consume prohibitive rack volume and copper. Reserve irreversible pathways for that DC architecture while keeping the rack-level fit-out generation-specific.

The design discipline mirrors the reversible/irreversible split from Part 1: pour the substation, MV ring, pathway, and floor-loading basis for the high-density DC endpoint you cannot retrofit, while fitting out the rack-level voltage architecture (which you can swap at refresh) to the generation you are actually buying. Build the chain for 40 kW and you have built an inference-only, current-generation building; reserve the headroom for the ramp and you keep the ramp open.

One more force reshapes topology before any of the above engineering is decided: what you can actually buy, and when. Power-chain equipment carries some of the longest lead times in the entire build, and in a power-bound market the lead time is the design constraint. HV and substation power transformers run ~128 weeks standard and generator step-up units ~144 weeks (Wood Mackenzie, Q2 2025), with US GSUs quoted at 3–4 years (~156–208 weeks) by mid-2026 (SemiAnalysis) and stretching to ~60 months in constrained markets (Wood Mackenzie). That delivery date is the schedule-dominating long pole that often decides energization. MV switchgear, large UPS modules, and SST/DC gear all carry multi-quarter-to-multi-year queues, and the newer DC-disaggregated equipment is precisely the thinnest-supplied.

Procurement therefore reshapes topology in two directions. First, it pulls toward fewer, more available stages — a topology that needs three exotic transformers you cannot get for four years is just a delay. Second, it can pull toward the DC path or away from it depending on the calendar: the AC-to-the-rack ecosystem is fully stocked today, while the SST/800 VDC ecosystem is ramping — so a 2026 ground-break may be forced onto AC distribution for the IT layer even as it builds the substrate for DC. Every long-lead power item belongs in the lead-time register maintained in Chapter 2.3, and the voltage architecture you commit to should be cross-checked against that register before it is frozen. A single-line is only as good as the delivery dates of its long-lead gear: equipment that energizes after the depreciation clock has started is a design failure, however elegant the drawing.