Subsystem Roadmaps 2026 → 2030 (Consolidated)

The forward-looking sections scattered through Parts 4 through 9 each end with the same uneasy sentence: this subsystem is about to replatform. Power is moving off AC. Cooling is moving off air, and single-phase liquid is already being framed as the floor rather than the ceiling. Fabric bandwidth roughly doubles each accelerator generation while memory capacity steps unevenly. The network is fighting a three-way standards war while optics migrate onto the package. Storage is being pulled into the GPU's memory hierarchy. All five sit downstream of the same accelerator roadmap, which is why they move in sync — five faces of the power-bound density ramp. This chapter consolidates those forward pointers into a single 2026 → 2030 view and sorts the moves you can defer from the ones you must commit before steel is cut.

A roadmap is a register of option premiums. Betting on the wrong generation of GPU is reversible only at the cost of new trays, qualification, software work and downtime; a next-generation tray is not an in-place upgrade entitlement. The expensive mistake of the 2026 era is building a substrate that cannot absorb the generation after next, because the floor, the water, the risers, and the voltage class are the things you cannot retrofit cheaply once the hall is live. We walk the five subsystems in the order the cascade flows — power, cooling, compute/memory, network/optics, storage — and close on the rack and facility integration that ties them together, because on the 2027–2028 roadmap the unit of design stops being the 19-inch rack and becomes the ~600 kW power-and-cooling chassis.

Buy a reservation with a release test. For NVIDIA, AMD, Google and AWS, compare the same fields: dated orderable system, power modes and facility basis, floor and service loads, coolant temperature/flow/chemistry, rack and connector interface, fabric boundary, software acceptance, support and delivery entitlement. A public NVIDIA roadmap, an AMD complete-system quote, Google TPU regional access and AWS service availability are different offers; none alone proves that your existing hall can accept new trays. Reserve space and routes where a bounded option premium is affordable, then release busway, CDU and IT orders only when a named system passes the interface and service tests. Reject the option when the reserved path still requires an unapproved voltage class, coolant or structural load: empty space cannot repair an incompatible interface. → engineering acceptance in Chapter 6.2, memory sizing in Chapter 7.6 and migration acceptance in Chapter 7.9.

The power chain is the subsystem under the most acute roadmap pressure, because it sits at the intersection of two exponentials: the per-rack power basis climbing from 132 kW nominal for HPE GB200 through 135 kW TDP / 155 kW peak for GB300 to 188 kW Max Q / 228 kW Max P for Vera Rubin, with a 330 kW facility design basis, and toward the ~600 kW Rubin Ultra/Kyber roadmap point, and the grid-side scarcity that made power the binding constraint in the first place (Chapter 16.1). At ~40 kW you can rectify AC inside the rack and not think about it. At MW-class scale, in-rack 54 VDC distribution hits physical and economic limits as copper and power-shelf volume crowd out compute. The roadmap answer is 800 VDC, delivered either from native facility distribution or from a row-level power rack fed by existing AC infrastructure.

The choice is between keeping 415/480 VAC to three-phase AC-input Rubin power shelves, using a row-level AC-to-800 VDC bridge that preserves existing building infrastructure, and committing a new MW-class hall to native 800 VDC distribution. In NVIDIA's three-wire-DC versus four-conductor-AC comparison, 800 VDC carries ~157% more power through the same copper than 415 VAC, and the SemiAnalysis May 26, 2026 SST/800 VDC architecture model puts end-to-end utility-to-VRM efficiency at ~87%. Chapter 4.1 owns the separate four-stage AC fixture (80.4–86.7%, 82.2% representative; distribution losses separate). Their roughly five-point numerical gap becomes recoverable capacity only after stage boundaries and load match; at 1 GW input, five verified efficiency points would deliver 50 MW more output. The catch is that the DC ecosystem is immature: the solid-state transformer (SST) is offered for medium-voltage-to-800 VDC conversion, but the ETH Zurich benchmark needs its primary test report before any efficiency or target is credited. Obtain the offered assembly’s listing and installation acceptance; a generic 2029 expectation establishes neither. The decision you face in 2026 is therefore whether to preserve AC infrastructure with an AC-input Rubin shelf or row-level 800 VDC bridge, or pay now for native 800 VDC distribution where the MW-class roadmap justifies it.

Underneath the distribution question sits the generation question. The interconnection wall has pushed behind-the-meter (BTM) on-site generation from a fringe tactic to a mainline strategy: ~90 GW of BTM gas has been announced cumulatively by mid-2026 (though only ~1 GW is under construction and ~2 GW online), because an on-site plant may beat the named utility’s service date when its turbine, fuel, permit and commissioning schedule closes first. Neither an 18–36-month turbine schedule nor a four-to-seven-year utility queue is a portable project promise. So the power subsystem is no longer just a distribution-engineering problem inside the fence — it is a generation, fuel-supply, and grid-interactive problem, and the building must be designed to host the generation it may need to bridge to grid power. → DC architecture in Chapter 4.7; on-site generation in Chapter 4.8; the queue and speed-to-power in Chapter 3.2.

Cooling crossed its decisive fork earlier than the other subsystems, and the roadmap reflects a settled near-term and a contested far-term. The near-term is clearer than the far-term: single-phase direct-to-chip liquid cooling is a mainstream 2026 path. One reported forecast is roughly 55%, but the published category is broader cold-plate cooling rather than a measured single-phase-DTC deployment share; dense NVL72-class racks require direct-to-chip liquid because their product heat splits and airflow/inlet limits leave no air-only path. That conclusion belongs to the named equipment and facility envelope, not a universal rack-kW threshold. The forward question is what comes after single-phase D2C when per-die thermal density keeps climbing toward and past 2 kW.

Here the roadmap forks into two candidate successors, shaped as much by chemistry and liability as by thermodynamics. Two-phase approaches (two-phase D2C and two-phase immersion) offer better heat transfer by exploiting latent heat of vaporization — but two-phase immersion stalled hard when the PFAS health-and-liability crisis drove 3M to exit the Novec fluorochemical business, leaving the supply chain and regulatory picture for the dielectric fluids deeply uncertain. Microfluidics — etching coolant channels directly into the silicon, as in Microsoft's research demonstrating up to ~3x cold-plate performance with AI-designed bio-inspired channels — is the more promising far-term path because it attacks the thermal resistance at its source (the die-to-coolant interface) rather than downstream of it. Neither is a 2026 production decision, so the conservative move is concrete: build for single-phase D2C now, but reserve the mechanical and facility-water headroom (CDU capacity, secondary-loop delta-T margin, manifold and quick-disconnect provisioning) so the hall retains an adoption option; the successor’s coolant chemistry, pressure, materials, water flow and service procedure must still pass a new qualification before anyone promises to avoid re-plumbing. → DLC in Chapter 5.4; immersion and the PFAS problem in Chapter 5.5; facility water loops in Chapter 5.7.

The accelerator roadmap sets the clock for every other subsystem in the building. The publicly-stated cadence is yearly: Vera Rubin (NVL72, 188 kW Max Q / 228 kW Max P) in 2026, Rubin Ultra in H2 2027 — deployed either as the NVL576 system (eight MGX NVL72-class racks in one 576-GPU optical NVLink domain) or in the ~600 kW Kyber rack (NVL144: 144 quad-die packages = 576 GPU dies; eight Kyber racks form NVL1152) (as announced at GTC 2026; by Aug 2026 the supply chain no longer treats these as the shipping plan — SemiAnalysis reported Kyber NVL144 slipping to 2028 on PCB-midplane manufacturability and NVIDIA replied only that "our roadmap is intact", while The Information/BofA/Mizuho report NVIDIA evaluating lower Rubin Ultra memory configs, so per-package specs and the Kyber timeline are in flux), ~15 ExaFLOPS FP4 inference / 5 ExaFLOPS FP8 training per rack — and Feynman in 2028, widely expected to push toward the 1 MW rack. Memory climbs in lockstep: per-GPU HBM goes H100 80GB → B200 SXM 180 GB → B300 288GB → Rubin 288GB HBM4 (shipping 2026) → Rubin Ultra, announced at 1TB HBM4e but as of Aug 2026 being evaluated in the 192–288 GB band under an HBM4e supply squeeze (BofA reads the cut as temporary and supply-driven, not a demand peak). For a strategist the takeaway is the cadence, not the spec sheet. A yearly generation step with a contested roughly 2–3-year frontier-economic bear case (the depreciation sensitivity from Chapter 1.8) means the substrate you pour in 2026 must absorb at least two generations of density growth within its first refresh window.

On first live silicon, CoreWeave measured a Vera Rubin NVL72 delivering up to ~10× the tokens per megawatt of a GB200 NVL72 (DeepSeek-R1 at a matched interactivity target), which NVIDIA pairs with one-tenth the inference cost per million tokens, up to 10× the inference per watt, and one-fourth the number of GPUs (~75% fewer) to train a given MoE model — a training metric. These are vendor ratios versus Blackwell, not absolute $/token: no absolute cost-per-token or tokens-per-dollar has been published.

The roadmap risk on this axis is the advanced-packaging gate, not the GPU. The binding constraint above wafer fabrication is TSMC CoWoS capacity and HBM stacking, not transistors. Contract HBM and CoWoS allocation against the delivery schedule; HBM4 is already in high-volume production for Vera Rubin. The consequence for a data-center program is counterintuitive: your delivery schedule is gated less by your capex and more by an upstream packaging line you do not control. A scope that assumes GPU availability on the vendor's stated cadence, without an allocation agreement, is underwriting a schedule it cannot guarantee. → NVIDIA roadmap in Chapter 7.2; HBM in Chapter 7.6; advanced packaging in Chapter 7.7.

The network roadmap is where the most consequential standards bet lives, because unlike power or cooling — where physics largely dictates the answer — the fabric question is partly a political one about which ecosystem you tie your accelerator optionality to. Two distinct fabrics are evolving in parallel. Scale-up (the high-bandwidth accelerator domain, which may span one rack or multiple racks) is the contested ground: NVIDIA's NVLink (1.8 TB/s/GPU on Gen5, 3.6 TB/s on Gen6) with NVLink Fusion opening the IP to third-party CPUs/XPUs; the open UALink / UALoE consortium path (UALink Consortium’s historical April 2025 1.0 release describes up to 1,024 accelerators; the maintained Common/DL-PL/Chiplet/Manageability catalogue identifies later revisions. UALink-over-Ethernet and native UALink switching have different implementation paths; an open specification alone does not establish deployed interoperability); and Broadcom's SUE/ESUN (Scale-Up Ethernet). Scale-out (the cluster fabric connecting independent scale-up domains) is consolidating faster around Ultra Ethernet (the maintained UEC specification; historical launch and implementation support remain separate in Chapter 8.4) as the open answer to InfiniBand, alongside NVIDIA's Spectrum-X — whose Rubin-generation switch, the 102.4 Tb/s Spectrum-6, is now arriving at named gigascale factories (CoreWeave, Microsoft, Nebius, OCI) with co-packaged optics available, so CPO is shipping in the top-of-fabric switch rather than only on the 2027 horizon.

The scale-up standard you underwrite is a multi-year lock-in decision: it sets which accelerators you can rack, how large a scale-up domain you can build (and therefore your tensor-/expert-parallel ceiling), and your copper-vs-optics reach budget. Choose NVLink and you get the largest, most mature scale-up domains and the deepest software stack — at the price of single-vendor accelerator dependence. Choose UALink or SUE and you preserve multi-vendor optionality at the price of a younger ecosystem and smaller proven domains. Underneath both sits the optics transition: as lane rates climb to 200G and 448G and reach budgets shrink (passive copper ~1–2 m at 800G/1.6T), co-packaged optics moves the optical engine onto the switch package — reducing the illustrated 1.6 Tb/s interface from ~30 W pluggable to ~9 W CPO (NVIDIA, August 18, 2025). The rounded component sums are 20 W DSP + 10 W laser versus 7 W optical engine + 2 W laser; 30/9 is about 3.3×. NVIDIA separately markets 3.5× power efficiency and 10× resiliency; those vendor architecture claims do not measure a whole fabric’s delivered-work energy. NVIDIA's Quantum-X (InfiniBand) reached availability in early 2026, and NVIDIA declared Spectrum-X Ethernet Photonics in production on 31 May 2026 (Chapter 8.10). If your 2027 build uses a ~600 kW Kyber rack, rack-to-rack optics and CPO are very likely on your critical path, not an option. → scale-out standards in Chapter 8.4; topology and oversubscription in Chapter 8.5; CPO and fiber plant in Chapter 8.10.

Storage is the subsystem most often left off a roadmap, and the most quietly transformed by the density ramp. The forward direction has four threads. First, the data path is moving off the CPU: GPUDirect Storage and GPU/DPU-initiated I/O let the accelerator pull data over NVMe-oF without a host-CPU bounce, and the new generation of DPUs (NVIDIA BlueField-4 at 800 Gb/s) is built to own this path. Second, the spinning disk is being designed out of the hot path entirely — all-flash is becoming the default for both the training scratch tier and the checkpoint tier, with PCIe 6.0 dense-flash servers (e.g. 96 E3.S SSDs, ~2.9 PB) emerging to feed it. Third, the historical split between parallel file systems and object stores is converging, as the same platforms (WEKA, VAST, DDN) serve file and object semantics over one flash substrate. Fourth, and most distinctively for inference, CXL and Ethernet-attached flash are becoming a KV-cache tier — a new layer of the memory hierarchy that sits between HBM and bulk storage.

That last thread is the one with the sharpest 2026 roadmap signal. As reasoning models emit long decode sequences, the KV cache balloons, and the economics of holding it in HBM collapse. The answer is a three-tier KV hierarchy — now productized as NVIDIA's CMX/STX, a BlueField-4-powered context-memory tier for the Rubin generation (a SuperPOD-scale complex pencils out at ~9.6 PB of NAND, 16 enclosures × 4 BlueField-4 × 150 TB per Chapter 9.7, making enterprise SSD a Rubin-generation BOM line and a source of NAND-spot pressure): HBM, then host/CXL memory, then NVMe and Ethernet-attached flash — that NVIDIA is standardizing via BlueField-4's context-memory platform (CMX) and the NIXL transfer library, with vendors reporting the ability to serve roughly 10x more users by offloading prefix caches to flash. For the facility, storage is no longer a back-of-house capacity question; it is part of the inference memory hierarchy and sits on the latency-critical path. A 2026 design that treats storage as bulk capacity, decoupled from the fabric and the accelerator, is designing for the training workload of 2023, not the inference workload of 2026. → the CPU-bypass data path in Chapter 9.3; inference and KV-cache storage in Chapter 9.7; object/capacity tier in Chapter 9.6.

The five subsystem roadmaps do not converge on a server — they converge on a chassis. The defining structural shift of 2026 → 2030 is that the unit of design stops being the 19-inch rack populated with independent servers and becomes an integrated power-and-cooling enclosure where compute, NVLink switching, liquid distribution, and power delivery are co-engineered as one mechanical object. The HPE GB200 NVL72 (132 kW nominal, with its own mass and power-distribution drawings; NVIDIA’s separate October 2024 OCP reference explains the over-5,000-cable copper backplane, blind-mate liquid manifolds and 1,400 A busbar design) is the first generation that can only be understood as a single integrated unit. GB300 NVL72 shipped in 2025 and is deploying through 2026 alongside GB200, with up to 142 kW as NVIDIA's facility design basis; VR200 NVL72 entered full production in August 2026 and operates at 188 kW Max Q / 228 kW Max P, while NVIDIA's DSX facility design basis provisions 330 kW per cabinet. The ~600 kW Kyber rack (NVL144) is the endpoint: at that power the disaggregated sidecar (Mt Diablo / Diablo 400) moves power conversion out of the compute rack into an adjacent power chassis, the busbar becomes liquid-cooled, and scale-up optics move onto the package.

For facility design this collapses several previously-independent decisions into one substrate commitment. A ~600 kW chassis — no vendor mass figure is published, but the ~132 kW NVL72 already weighs ~3,000–3,300 lb wet, so Kyber-generation racks will land substantially heavier — implies a structural slab and seismic-anchoring basis you cannot retrofit (Chapter 6.2, Chapter 6.7); an 800 VDC riser and busway you cannot rip out without a hall outage; a facility-water capacity and pipe-rack geometry sized for liquid heat rejection at that density; and a row-and-aisle pitch set by the chassis footprint plus its sidecar. The same rule applies here as across the whole roadmap: reserve the irreversible substrate for the chassis you will house in 2027–2028, and keep the reversible fit-out — the actual trays, transceivers, CDUs, and storage shelves — matched to the generation you are buying this year. → rack as integration unit in Chapter 7.13; modular/prefab construction in Chapter 6.4.

Read the document cover before freezing an interface: ORv3 Base, ORW Base and ORW Meta Design are separate documents, not interchangeable rack approvals. The UALink component catalogue separates Common, DL/PL, Chiplet and Manageability specifications; implemented interoperability still needs the named fabric test. TIA’s AI addendum development announcement is not a published compliance requirement. Carry those document identities into the purchase specification, then apply the rack and software acceptance in Chapter 7.13 and Chapter 7.9.