CoWoS · Chip-on-Wafer-on-Substrate
TSMC's 2.5D packaging that joins logic die and HBM stacks on a silicon interposer; its wafer capacity gates AI supply.
TSMC advanced-packaging process integrating compute and memory on an interposer; an upstream supply chokepoint.
Also written as: Chip-on-Wafer-on-Substrate
Current numbers
~600 kWRubin Ultra Kyber rack (NVL144) on 800 VDC — GTC 2026 also defined NVL576 as an eight-rack MGX system; supply-chain reports (Apr–Jun 2026) say the package was cut to dual-die 2+2 over CoWoS-L warpage, unconfirmed by NVIDIA
~120–140k wafers/monthTSMC CoWoS capacity in 2026, from ~75–80k wafers/month; +50–60k at OSAT partners (TrendForce, June 2026)
~1.0M wafers2026 CoWoS allocation implied by reported shares: NVIDIA ~60%, Broadcom ~15%, AMD ~11% (May 2026)