The Definitive Guide toAI Data Centers
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ICI · Inter-Chip Interconnect

Google's TPU scale-up link, wiring chips into a torus instead of an all-to-all crossbar, so coherent domain size comes from topology and optical switching rather than a central switch tier.

Current numbers

9,216 chipsGoogle Ironwood (TPU v7) scale-up superpod via ICI (9.6 Tb/s/chip) + OCS (48 units, 13,824 ports)as of 2026 · register ↗

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