GPUs reachable in a two-tier fabric of 51.2 Tb/s (512x100G) switches when each 800G NIC is split by lane into eight 100G ports, one per independent plane — the multiplanar design published by the MRC consortium, which reports deployed four-plane (4×200G) and eight-plane (8×100G) systems; NVIDIA's multiplane analysis reaches the same ~128K two-tier scale
131,072derived
| Value kind | derived — Derived values are guide calculations; their result is only as fixed as the stated inputs, scope, and method. |
|---|---|
| Scope | Eight-plane design maximum in the May 2026 MRC/SRv6 paper, which reports deployed four-plane (4 × 200G) and eight-plane (8 × 100G) MRC systems. |
| Caveat | 131,072 = 512 T0 switches × 256 NICs in each of the 8 planes, with every GPU holding one 100G port per plane (design maximum); the consortium paper reports deployed four-plane (4 × 200G) and eight-plane (8 × 100G) systems. |
| As of | 2026-05 |
| Source | Consortium production/design paper, May 2026. |
| Derivation | 512 leaves ×256 endpoints =131072 endpoints per plane; eight100G attachments per endpoint aggregate800G. Full usable radix and symmetric wiring assumed. |
| Review | checking…review by 2026-09-30 · standard cadence |
| Recorded changes | last 2026-09-16 · 3 revisions tracked |
| Claim id | mrc-eight-plane-two-tier-gpu-scale |
Where the guide uses it
← Full numbers register — every date-stamped figure in the guide, with revision history.